Abstract: A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals.

Abstract: Gate speed evaluation circuitry evaluates the operating speed of gates of a calibration network and adjusts the length of a tapped delay network on the same chip to provide uniform delay in a signal.

Abstract: The voltage across the primary of the ignition coil of a spark ignition engine is limited so as to defeat ignition, while at the same time allowing measurement of ignition-related signals, by means of unilateral impedance means which are selectively connected by a switch in parallel with the ignition coil primary, to service engines both with and without series impedance in the low coil signal line. To avoid reversed-polarity connection, the switch is operable only if the average voltage between high coil and low coil connections indicate correct polarity. Sensing of high coil and low coil signals indicative of firing time and dwell is achieved by monitoring current flow through the unilateral ignition defeat impedance, by means of an optical isolator resistively coupled across the unilateral impedance; current in the optical isolator is limited by means of a shunt transistor, and the optical isolator is protected against high voltages by an additional unilateral impedance.

Abstract: The end of the dwell period of a spark ignition engine is recognized by a high voltage, spark-creating swing in the low coil signal determined from comparison with a first, fixed threshold voltage which is above the current limited voltage variation of modern electronic high voltage ignition systems and a low peak primary voltage normally achieved with ignition defeat used in other diagnostic procedures. The beginning of the dwell period is sensed by comparing the low coil signal to the actual battery voltage of the engine under test; the comparison is against a substantial fraction of battery voltage which will always exceed any low coil voltage which could exist during the dwell period.

Abstract: The signal indicative of switching of the ignition primary coil of a spark ignition engine is conditioned by means of compatible, combined, multiple and variable threshold testing of both the high end and the low end of the coil primary, without need to know (or alter operation in dependence upon) whether the engine employs positive switching at the high end of the primary coil or negative switching at the low end of the primary coil. To sense the end of the dwell period, the high coil voltage is compared against a negative voltage which will never occur if low coil switching is employed, but which will occur at the start of firing time in a positive switching system. Similarly, low coil is compared against a positive voltage which would never occur in a positively switched system, but which does occur at the start of firing time if negative switching is used.