Patents by Inventor Paul R. Bie

Paul R. Bie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4935805
    Abstract: On a semiconductor substrate (14, 38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: June 19, 1990
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, David Ward
  • Patent number: 4923827
    Abstract: On a semiconductor substrate (38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated with the remaining portions of the contact structure being masked by selective oxidation.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: May 8, 1990
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, David Ward
  • Patent number: 4876176
    Abstract: Method for fabrication of quasi-monolithic microwave integrated circuits in which metals, oxides, and processes are selected to enable fabrication of the circuits by first producing many layers of metals and oxides in situ without removing the circuit from its environmental chamber. This reduces inclusion of contaminating chemical films and particles between the desired layers. Circuit elements are then defined by processing of the layers by photolithography and other processes from the top of the circuit downward. Lumped and distributed capacitors, resistors, inductors, transmission lines, and contacts for active devices are monolithically defined, with a reduced number of process steps.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: October 24, 1989
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, Ronald J. Pomian
  • Patent number: 4789645
    Abstract: During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: December 6, 1988
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, Ronald J. Pomian