Abstract: Small voltage changes on a highly capacitive signal are sensed rapidly by placing a shielding impedance between the signal to be sensed and the input to a regenerative sense circuit. A regenerative sense circuit has a sense amplifier which controls a switching means that is connected to the input to the sense amplifier. When the output of the sense amplifier reaches a threshold value, it turns the switching means on. This switching means increases the rate of change on the input to the sense amplifier which causes the switching means to turn on even more. The input and output of the sense amplifier are able to switch more rapidly because the shielding impedance allows the switching means to change the state of the input to the sense amplifier without having to completely change the voltage level on the highly capacitive input signal. A small voltage difference between two signals is sensed by two cross-coupled, actively loaded, NMOS inverters.

Abstract: Small voltage changes on a highly capacitive signal are sensed rapidly by placing a shielding impedance between the signal to be sensed and the input to a regenerative sense circuit. A regenerative sense circuit has a sense amplifier which controls a switching means that is connected to the input to the sense amplifier. When the output of the sense amplifier reaches a threshold value, it turns the switching means on. This switching means increases the rate of change on the input to the sense amplifier which causes the switching means to turn on even more. The input and output of the sense amplifier are able to switch more rapidly because the shielding impedance allows the switching means to change the state of the input to the sense amplifier without having to completely change the voltage level on the highly capacitive input signal. A small voltage difference between two signals is sensed by two cross-coupled, actively loaded, NMOS inverters.

Abstract: A register sub-circuit for a logic system is described which is capable of loading a logic signal from a bus, holding the state of the logic signal, and dumping the logic signal onto a precharged high capacitance bus. The circuit is master/slave in operation permitting the register to simultaneously dump the current contents of the register at the same time a new value is being loaded into the register. The circuit operates with a single phase clock. The circuit is easily integratable. The circuit comprises a storage sub-circuit and one or more dump sub-circuits. The circuit presents a low capacitance load to the dump control line.