Abstract: A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.

Abstract: Systems and methods are disclosed for providing a multi-stage interconnect architecture, such as for high density and high performance complex programmable logic devices. As an example, a first stage of a two-stage interconnect architecture programmably routes signals from a global routing structure to a second stage of the two-stage interconnect architecture. The second stage routes signals from the first stage to a number of logic blocks. The second stage also-optionally routes feedback signals from the logic blocks along with signals from associated I/O terminals back to the logic blocks to provide local feedback capability.

Abstract: Cascadable logic block architectures are disclosed for programmable logic devices, such as for high density and high performance complex programmable logic devices. The logic block architectures provide, for example, clusters or groups of logic blocks that may have cascadable inputs and/or product terms to provide flexible logic width and/or depth capability. The logic block architecture may, for example, be implemented in conjunction with a multi-stage interconnect architecture to provide array fuse density and/or interconnect fuse density savings compared to conventional architectures.