Abstract: The present invention relates to 12 novel human secreted proteins and isolated nucleic acids containing the coding regions of the genes encoding such proteins. Also provided are vectors, host cells, antibodies, and recombinant methods for producing human secreted proteins. The invention further relates to diagnostic and therapeutic methods useful for diagnosing and treating disorders related to these novel human secreted proteins.

Abstract: The present invention relates to 12 novel human secreted proteins and isolated nucleic acids containing the coding regions of the genes encoding such proteins. Also provided are vectors, host cells, antibodies, and recombinant methods for producing human secreted proteins. The invention further relates to diagnostic and therapeutic methods useful for diagnosing and treating disorders related to these novel human secreted proteins.

Abstract: The present invention relates to 12 novel human secreted proteins and isolated nucleic acids containing the coding regions of the genes encoding such proteins. Also provided are vectors, host cells, antibodies, and recombinant methods for producing human secreted proteins. The invention further relates to diagnostic and therapeutic methods useful for diagnosing and treating disorders related to these novel human secreted proteins.

Abstract: A CMOS cell and circuit design methodology for improved IDDQ testing for logic and memory circuits. The CMOS cell library includes one or more CMOS cells, each including one or more PMOS and NMOS transistors. Each CMOS cell is configured to assert its outputs high during a high test portion of a test mode in which each input is asserted high. Each CMOS cell is configured to assert its outputs low during a low test portion of the test mode in which each input is asserted low. At least one CMOS cell of the library includes one or more test transistors, each test transistor receiving one of first and second test inputs. The test inputs indicate a normal mode, a high test mode and a low test mode. In this manner, each CMOS cell is configured so that each gate oxide interface of each transistor of the CMOS cell receives a test voltage during the test mode.

Abstract: A method and implementing circuit for converting a digital signal to an analog equivalent by providing a pulse width modulated (PWM) output signal in various formats which result in an analog equivalent signal with a substantially lower harmonic distortion profile. Counter circuitry (e.g. 301-305) with input registers (e.g. 307-311) are implemented to establish switching points at predetermined count values (e.g. 4C3) within the period of an output signal (PWM OUTPUT). In one embodiment, delay circuitry (303, 309) is effective to delay the beginning of an output pulse so that the pulse is centered, or otherwise selectively positioned within an output signal period to minimize harmonics, and the pulse duration is set to correspond to a digital value to be converted. In other implementations, subcycles are defined and output pulses are established within such subcycles to provide the low harmonic output signal while maintaining an analog equivalence value of a digital input.

Abstract: A multiplexer circuit (100) having N data inputs (151, 152, 156) is operable for outputting one of the received N data inputs (151, 152, 156) to its data output (150) in response to receipt of a plurality of control signals (144), which are produced by encoding (143) the selection signals (145) typically implemented for controlling such a multiplexer circuit (100).

Abstract: A multiplier circuit (300, 400, 500, 600) uses a horizontal pipelining of the circuitry (301, 401, 501, 601) in order to reduce the number of gate-drain delays within the various data paths through the array (301, 401, 501, 601). Additionally, a combination of vertical and horizontal pipelining (550, 650) may also be implemented. The multiplier circuit (400, 600) may implement a modified Booth's algorithm. A horizontal pipeline latch (350, 450, 550, 650) operates to divide the array (301, 401, 501, 601) into two portions, where the first portion (360, 460, 560, 660) operates on the least significant bits of the resulting product, while the second portion (361, 461, 561, 661) operates on the most significant bits of that product.