Abstract: A method is presented for generating a timing model for a logic cell. Output load indices (Load1, Load2, . . . ,Loadm) are selected which specify output load for the first logic cell. Input ramp indices (IR1, IR2, . . . ,IRn) are selected which specify input ramp for the first logic cell. Baseline output ramp values (ORbl [j,k]) are generated for each output load index (Loadj) and input ramp index (IRk) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (&lgr;). The input ramp indices are scaled by a second scaling factor (&rgr;). Scaled output ramp values (ORscaled [j,k]) are generated for each scaled output load index and scaled input ramp index pair.

Abstract: Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.

Abstract: Computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described. In one embodiment, the physical design comprises a plurality of layered conductors which are disposed within a first dielectric material. At least one conductor of the plurality of conductors is identified, and for the identified conductor, the first dielectric material is replaced for calculational purposes with a second (fictitious) dielectric material having a dielectric constant which is higher than the dielectric constant of the replaced dielectric material. In general, the second dielectric may have a different dielectric constant for each identified layer or elevation. Parasitic capacitance values are then computed for the integrated circuit. In a preferred embodiment, spaced-apart conductors at a common substrate elevation are identified, and a distance between the conductors is determined.

Abstract: Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilcon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.