Abstract: A method and apparatus for applying a wear coating to the back side of a wear part.

Abstract: A method and apparatus for applying a wear coating to the back side of a wear part.

Abstract: A method and apparatus for applying a wear coating to the back side of a wear part.

Abstract: A hammer and hammer tip combination is provided for use with a size reducing machine, and comprises a hammer body having a nose extending up to and defining a lower edge of a debris path; a protective pocket located behind the nose relative to the debris path; and a hammer tip releaseably secured to the hammer body and located behind the protective pocket relative to the debris path.

Abstract: The present invention intends to overcome the difficulties encountered heretofore. To that end, a size reducing machine with a rotating tub having a guide wheel with a cover for rotateably engaging the rotating tub is provided. The machine comprises a rotating tub having an open top, side walls, and a floor with an opening located therein, a rotary hammermill located substantially below the opening in the floor of the rotating tub, a drive mechanism for rotating the tub, a frame for operationally supporting the frame and the drive mechanism, a guide wheel rigidly attached to the frame and rotateably engaged with the rotating tub, and a guide wheel cover for protecting operational components of the guide wheels from failure induced by accumulation of debris from the size reducing machine and surrounding environment.

Abstract: A face plate is provided for releasable attachment between a hammer and a hammer tip of a size reducing machine. The face plate provides a buffer between the hammer and the hammer tip. The hammer has a body with a forward facing hammer face that aligns with the back of the face plate. The front of the face plate aligns with the back of the hammer tip. The hammer, hammer tip, and face plate contain aligned bolt holes for receipt of a securement bolt that releasably secures the hammer, face plate, and hammer tip. The face plate includes a center section raised above opposing ledges designed for mated alignment with a recessed center section of the back of the hammer tip.

Abstract: The invention comprises a rotor and hammer assembly comprising a drive shaft allowing for rotating the rotor and hammer assembly. End plates are secured to the drive shaft, and a rotor casing is secured to the end plates. The rotor casing has an outside surface, to which a hammer is removably secured. The outer surface of the rotor casing includes slots, having a first and second slot section with a raised center portion therebetween. The hammer has a substantially flat base with a centrally located notch, such that the hammer base and the slot matingly align. The hammer is further secured to the outer surface of the rotor casing with threaded bolts. The hammer includes a front face with a raised center section and recessed comers that matingly align with the hammer tip, and is further secured with threaded bolt and nut.

Abstract: A hammer comprising a hammer body. The hammer body comprises a rotor forming portion with a trailing and a leading edge and is capable of securement to a rotor, a tip support section capable of extending into a debris path, and a production pocket extending from the leading edge of the rotor portion also capable of extending into the debris path. The hammer also comprises a hammer tip secured to the tip section of the hammer body and at least partially shielded from the debris path by the production pocket of the hammer body.

Abstract: A hammer and rotor assembly for a size reducing machine. The rotor of the assembly comprises a drive shaft for rotating the assembly. The drive shaft includes a drive end and an outboard end, wherein the drive end secures to the drive motor of the size reducing machine. End plates secure the drive end and outboard ends of the drive shaft, and a center support also secures to the drive shaft. A rotor casing is secured to the end plates and the center support. The assembly includes a plurality of hammers having a hammer body with a rotor forming portion capable of securement to the rotor casing, a tip support portion extending into the debris path from the rotor forming portion of the hammer body. The hammer body also includes a production pocket. A rotatable hammer tip with a working edge and a protected edge is secured to the tip support section of the hammer body such that the hammer tip is at least partially shielded from the debris path by the production pocket.

Abstract: A hammer comprising a hammer body. The hammer body comprises a rotor forming portion with a trailing and a leading edge and is capable of securement to a rotor, a tip support section capable of extending into a debris path, and a production pocket extending from the leading edge of the rotor portion also capable of extending into the debris path. The hammer also comprises a hammer tip secured to the tip section of the hammer body and at least partially shielded from the debris path by the production pocket of the hammer body.

Abstract: A rotor assembly for use with size reducing machines having a drive motor comprising a central shaft with a drive end for securement to the drive motor and an opposing outboard end. The rotor assembly also comprises a webbing engaged with the central shaft for supporting the rotor assembly, a rotor casing substantially seals the webbing, and a plurality of sockets secure to a plurality of casing throughbores. The webbing comprises a drive end plate secured to the central shaft with a bushing, an outboard end plate secured to the central shaft with a bushing, and a plurality of web socket supports aligned in two transversely aligned rows. The web socket plates each comprise two socket receiver channels for alignment with the sockets. Finally, a plurality of hammers releasably secure to the plurality of sockets.

Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.

Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit uses an active integrator. The integrator has a left-half plane pole. A feedback path is provided that includes a resistive impedance which comprises a MOS transistor operated in the triode region. The resistive impedance is adjustable for cancelling the pole. The feedback path also includes a capacitive impedance coupled in series with the resistive impedance.

Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2 Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mbps, and is built in a 1.5.mu./4 GHz BiCMOS technology.

Abstract: A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.

Abstract: This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.

Abstract: A flash ADC utilizes parallel weighted capacitive arrays and a resistor string to provide reference voltage intervals and an encoder for indicating the reference voltage interval wherein an input voltage lies. For an embodiment having N branches, the reference voltage intervals are subdivided into N sub-intervals and each succeeding clock cycle.

Abstract: An algorithmic analog-to-digital and digital-to-analog converter 10 combines the techniques of switched capacitor cyclic conversion by using first and second amplifiers 31, 32 with capacitors C.sub.1, C.sub.1 ', C.sub.2, C.sub.2 ', C.sub.3, C.sub.3 ', C.sub.4, C.sub.4 ', C.sub.5, C.sub.5 ' communicating with the inputs of said amplifiers 31, 32 and between the inputs and outputs of said amplifiers 31, 32, and the techniques of reference voltage refreshing. The performance of the converter 10 is capacitor ratio-independent. Because of the ratio-independent aspect, very small component values can be used, and as a result, the die area required for the circuitry can be quite small.

Abstract: An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

Abstract: A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.