Patents by Inventor Paul R. Hartmann
Paul R. Hartmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7434139Abstract: Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are modified in the first framed digital signal to generate a second framed digital signal, such that the modification is equivalent to insertion of errors into the first framed digital signal at a bit error ratio (BER) of not greater than a predetermined ratio, if the first framed digital signal indicates a failure. The second framed digital signal is then sent from the network interface in place of the first framed digital signal to indicate that the failure reported by the first framed digital signal is located in the customer premises equipment. Otherwise, if no failure is indicated, the first framed digital signal is transmitted without any modifications.Type: GrantFiled: May 26, 2005Date of Patent: October 7, 2008Assignee: Acterna, LLCInventors: Bruce R. Barton, Paul R. Hartmann, Maynard A. Wright
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Patent number: 7304958Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a “Sectionalizer Report”. In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated.Type: GrantFiled: July 10, 2002Date of Patent: December 4, 2007Assignee: Acterna LLCInventors: Derek J. Nelson, Paul R. Hartmann, Edward S. Tyburski
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Patent number: 6910167Abstract: Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are modified in the first framed digital signal to generate a second framed digital signal, such that the modification is equivalent to insertion of errors into the first framed digital signal at a bit error ratio (BER) of not greater than a predetermined ratio, if the first framed digital signal indicates a failure. The second framed digital signal is then sent from the network interface in place of the first framed digital signal to indicate that the failure reported by the first framed digital signal is located in the customer premises equipment. Otherwise, if no failure is indicated, the first framed digital signal is transmitted without any modifications.Type: GrantFiled: August 15, 2002Date of Patent: June 21, 2005Assignee: Acterna LLCInventors: Bruce R. Barton, Paul R. Hartmann, Maynard A. Wright
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Publication number: 20030097624Abstract: Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are modified in the first framed digital signal to generate a second framed digital signal, such that the modification is equivalent to insertion of errors into the first framed digital signal at a bit error ratio (BER) of not greater than a predetermined ratio, if the first framed digital signal indicates a failure. The second framed digital signal is then sent from the network interface in place of the first framed digital signal to indicate that the failure reported by the first framed digital signal is located in the customer premises equipment. Otherwise, if no failure is indicated, the first framed digital signal is transmitted without any modifications.Type: ApplicationFiled: August 15, 2002Publication date: May 22, 2003Inventors: Bruce R. Barton, Paul R. Hartmann, Maynard A. Wright
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Publication number: 20030043753Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a “Sectionalizer Report”. In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated.Type: ApplicationFiled: July 10, 2002Publication date: March 6, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Derek J. Nelson, Paul R. Hartmann, Edward S. Tyburski
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Patent number: 6421323Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a “Sectionalizer Report”. In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated.Type: GrantFiled: September 12, 1996Date of Patent: July 16, 2002Assignee: Applied Digital Access, Inc.Inventors: Derek J. Nelson, Paul R. Hartmann, Edward S. Tyburski
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Patent number: 6091712Abstract: A method and apparatus for storing and communicating information regarding the condition of signals which pass through the network interface between customer premises equipment and a local exchange carrier in a telecommunications system. Information stored at the network interface can be sent as a message which is encoded within the payload, within the frame bits, or within the data link. The information that is stored at the network interface is sectionalized to reduce the amount of information that need be sent and to reduce the processing required by the receiving device.Type: GrantFiled: December 24, 1996Date of Patent: July 18, 2000Assignee: Applied Digital Access, Inc.Inventors: Kevin T. Pope, Maynard A. Wright, Daniel A. Strich, Paul R. Hartmann, Edward T. Ellebracht, Douglas B. Ramsayer
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Patent number: 5956324Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: October 30, 1997Date of Patent: September 21, 1999Assignee: Applied Digital Access, Inc.Inventors: Thomas L. Engdahl, Paul R. Hartmann, Kevin Pope, Kevin Cadieux
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Patent number: 5875217Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: February 23, 1999Assignee: Applied Digital AccessInventors: Paul R. Hartmann, Kevin Pope, Kevin Cadieux
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Patent number: 5790531Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. A Remote Alarm Indication-Customer Installation signal is generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: August 4, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5774456Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. Supplimental Performance Report Messages are generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: June 30, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5757776Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. An Alarm Indication Signal-Customer Installation signal is generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: May 26, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5703871Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: December 30, 1997Assignee: Applied Digital AccessInventors: Kevin Pope, Paul R. Hartmann
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Patent number: 5691976Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: September 7, 1993Date of Patent: November 25, 1997Assignee: Applied Digital AccessInventors: Thomas L. Engdahl, Paul R. Hartmann, Kevin Pope, Kevin Cadieux
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Patent number: 5623480Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and substrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: April 22, 1997Assignee: Applied Digital Access, Inc.Inventors: Paul R. Hartmann, Thomas L. Engdahl, Kevin Cadieux, Kevin Pope
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Patent number: 5621720Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel.Type: GrantFiled: February 14, 1996Date of Patent: April 15, 1997Assignee: Applied Digital Access, Inc.Inventors: Jeffery S. Bronte, Mark J. Lever, Kevin T. Pope, Paul R. Hartmann
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Patent number: 5602828Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: February 11, 1997Assignee: Applied Digital AccessInventors: Thomas L. Engdahl, Paul R. Hartmann, Kevin Pope, Kevin Cadieux
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Patent number: 5581228Abstract: A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: December 3, 1996Assignee: Applied Digital Access, Inc.Inventors: Kevin Cadieux, Paul R. Hartmann, Kevin Pope
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Patent number: 5566161Abstract: An improved network interface unit (NIU) for remotely monitoring and testing the performance of DS1 telephone circuits, installed on the network side of an interface between customer premises equipment (CPE) and equipment provided by the network provider. The inventive NIU is used to non-intrusively collect and transmit full-time performance monitoring data to the network provider. The inventive NIU provides continuous and non-intrusive performance monitoring of DS1 transmission systems. With the inventive NIU installed at the interface between the customer's CPE and the LECs' equipment, network service providers are alerted to potential problems before they adversely affect the service provided by the network providers to their customers. The inventive NIU enables a network service provider to quickly and non-intrusively determine whether a problem exists in the equipment provided by the network provider or in the equipment on the customer's premises.Type: GrantFiled: December 23, 1994Date of Patent: October 15, 1996Inventors: Paul R. Hartmann, Raymond L. Behr, George A. Wissing, Robert G. Young, Ramone A. Hecker, Maynard A. Wright, Edward T. Ellebracht
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Patent number: 5557616Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: September 17, 1996Assignee: Applied Digital Access, Inc.Inventors: Kevin Cadieux, Paul R. Hartmann