Abstract: Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIFO buffer to allow rapid sequential transfers; while also providing a flexible input/output configuration allowing both single-ended and differential mode connections.

Abstract: A system for managing data errors and media defects on magnetically and optically encoded disks. The invention is a disk controller utilizing a cylinder-based defect management system that reduces the amount of physical media space needed for bad block data replacement blocks. A unique attribute is calculated for and stored with each data block on each track that permits the controller to rapidly determine if a desired data block is in the current track. Spare blocks within a cylinder may be allocated to any track within that cylinder, permitting the system to more efficiently handle larger media or data errors than prior art devices that are limited to a particular number of spare blocks per track. When a bad data block occurs, the data from that block and all subsequent blocks is "slipped" to succeeding data blocks, thereby preserving the contiguity of the logical data structure and minimizing disk access time.