Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: Methods and apparatus are provided for processing information items. Processing comprises one of context filtering, context prioritizing, or both context filtering and context prioritizing. In some embodiments the set of context items from which processing criteria are derived includes a user's calendar of appointments, schedule changes, exceptions, and the like.

Abstract: A method and apparatus for attempting to contact at least one person in response to an event if the level of importance of the event to a first person meets or exceeds one threshold.

Abstract: A method and apparatus for escalating messages to a user concerning events of importance to the user comprising receiving information concerning an event, evaluating its importance to the user, and if the event is determined to be important enough for the user to be contacted, selecting a first way of contacting the user and using that first way to do so, waiting for a period of time for the user to respond, and if the user does not respond, selecting a second way of contacting the user and using that second way to do so.

Abstract: A method and apparatus for taking action in response to an event without contacting at least one person if the level of importance of the event to a first person meets or exceeds one threshold, but is below or only meeting another threshold.

Abstract: A source routing communication network of arbitrary topology communicates a message that includes header information. The communication network includes a plurality of routers, each router including a plurality of input/output ports and adapted to receive and send messages. Each router determines which output port of the router to send a router received message based on a portion of the header information. The communication network also includes a plurality of nodes adapted to receive and send messages. Each node is coupled to one of the routers, and modifies the header information of a node received message so that the header information provides a return route to the source node of the node received message.

Abstract: A method and apparatus for deadlock-free routing around an unusable routing component in a network reroutes paths between source and destination nodes by initially identifying an unusable routing component. A shadow direction within the network is then determined, the shadow direction being from the unusable routing component to an edge of the network. The paths between nodes are then rerouted so that the paths bypass the unusable routing component and limit the use of any routing components in the network between the unusable routing component and the edge in the shadow direction.

Abstract: A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.

Abstract: A parallel processing system virtual connection method and apparatus with protection and flow control is described. In accordance with the present invention, virtual connections between processor nodes are maintained through the use of connection tables. Each connection table is comprised of a plurality of connection table entries with each entry defining one end of a virtual connection between two processor nodes. Each connection table entry, in turn, comprises a data structure which stores data used to define the virtual connection. The passage of messages or data is accomplished through the use of the data structures within each connection entry in conjunction with message passing hardware in the node. User processes in the processor nodes interact directly with the message passing hardware, without the need to call the operating systems.

Abstract: An improved method of executing a plurality of computer application programs on a multicomputer is disclosed. The present invention pertains to a task scheduling system in a multicomputer having nodes arranged in a network. The present invention comprises an allocator and scheduler component, which comprises processing logic and data for implementing the task scheduler of the present invention. The allocator and scheduler operates in conjunction with a partition to assign tasks to a plurality of nodes. A partition is an object comprising a plurality of items of information and optionally related processing functions for maintaining a logical environment for the execution of tasks of one or more application programs. Application programs are allowed to execute on one or more nodes of a partition. Moreover, a node may be assigned to more than one partition and more than one application program may be loaded on a single node.