Patents by Inventor Paul R. Schroeder

Paul R. Schroeder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10710032
    Abstract: A universal wall and bridge mounted aeration apparatus has a track extending between two distinct elevations that is coupled to a wall and bridge mount. An aeration unit is pivotally coupled to the track and has an aerator adapted to operatively at least partially submerge within and aerate a liquid. A selective mover or drive is adapted to operatively move the aeration unit along the track and thereby vary an elevation of the aeration unit. The universal wall and bridge mount supports the track and aeration unit. The universal wall and bridge mount has a first configuration for mounting to a structure such as a stationary bridge, and a second configuration for mounting to a wall. The universal wall and bridge mounted aeration apparatus may be adjusted to position the propeller after installation under the surface of the liquid through three axes of motion freedom.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 14, 2020
    Assignee: Aeration Industries International, LLC
    Inventors: Randy W. List, Jing Huang, Joseph F. Widman, Brian J. Cohen, Todd M. Schroeder, Gregory R. Harding, Paul P. Gorbunow, Jason L. Jones, Steven R. Carleton
  • Patent number: 4477739
    Abstract: A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row.
    Type: Grant
    Filed: July 27, 1982
    Date of Patent: October 16, 1984
    Assignee: Mostek Corporation
    Inventors: Robert J. Proebsting, Paul R. Schroeder
  • Patent number: 4328563
    Abstract: The disclosed read only memory is formed in a two-dimensional matrix comprised of active areas disposed in parallel columns and of conductive layers disposed in rows transverse to the columns. A field-effect transistor is formed at each intersection of a column and a row. The rows of conductive layers are closely packed so that adjacent transistor channels abut one another.
    Type: Grant
    Filed: April 2, 1980
    Date of Patent: May 4, 1982
    Assignee: Mostek Corporation
    Inventor: Paul R. Schroeder
  • Patent number: 4296480
    Abstract: A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.
    Type: Grant
    Filed: August 13, 1979
    Date of Patent: October 20, 1981
    Assignee: Mostek Corporation
    Inventors: Sargent S. Eaton, Jr., Paul R. Schroeder
  • Patent number: 4156938
    Abstract: A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: May 29, 1979
    Assignee: Mostek Corporation
    Inventors: Robert J. Proebsting, Paul R. Schroeder
  • Patent number: 4110841
    Abstract: A low power high sensitivity detector having two pairs of cross coupled transistors and voltage equalization circuitry forms the basic configuration of a detector-level shifter circuit and a sense-refresh detector circuit which are both compatible with today's single chip large capacity MOS memories.
    Type: Grant
    Filed: December 6, 1977
    Date of Patent: August 29, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Paul R. Schroeder
  • Patent number: 4096402
    Abstract: An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: June 20, 1978
    Assignee: Mostek Corporation
    Inventors: Paul R. Schroeder, Robert J. Proebsting
  • Patent number: 4061954
    Abstract: An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a variable resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other digit line. As a result, one of the digit lines has a slightly higher voltage than the other.
    Type: Grant
    Filed: November 8, 1976
    Date of Patent: December 6, 1977
    Assignee: Mostek Corporation
    Inventors: Robert J. Proebsting, Paul R. Schroeder
  • Patent number: 4061999
    Abstract: An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a varible resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other line. As a result, one of the digit lines has a slightly higher voltage than the other.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: December 6, 1977
    Assignee: Mostek Corporation
    Inventors: Robert J. Proebsting, Paul R. Schroeder
  • Patent number: 4061933
    Abstract: A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: December 6, 1977
    Assignee: Mostek Corporation
    Inventors: Paul R. Schroeder, Robert J. Proebsting