Abstract: In a multiprocessor system, a plurality of data processors are each equipped with a local, level 1, cache and have access to a main memory through memory access circuit having a level 2 cache and a single register arbiter. The single register includes a primary queue defining priority of requests from the plurality of processors and a secondary queue defining processor requiring access to main memory. The register contains one position for each of the processors served and employs a pointer for demarcation between the primary and secondary queues. When a request is detected, the highest priority processor in the primary queue is served and when the requested memory address is in the level 2 cache, it will be retrieved and the identity of the served processor will be moved to the low end of the primary queue as defined by the pointer.