Patents by Inventor Paul R. Start
Paul R. Start has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804470Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.Type: GrantFiled: August 22, 2019Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Xavier F. Brun, Kaizad Mistry, Paul R. Start, Nisha Ananthakrishnan, Yawei Liang, Jigneshkumar P. Patel, Sairam Agraharam, Liwei Wang
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Publication number: 20230197574Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: ApplicationFiled: February 17, 2023Publication date: June 22, 2023Inventors: Aditya S. VAIDYA, Ravindranath V. MAHAJAN, Digvijay A. RAORANE, Paul R. START
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Patent number: 11587851Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: GrantFiled: May 18, 2021Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Publication number: 20210272881Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Aditya S. VAIDYA, Ravindranath V. MAHAJAN, Digvijay A. RAORANE, Paul R. START
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Patent number: 11049798Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: GrantFiled: June 28, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Publication number: 20210057381Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Xavier F. BRUN, Kaizad MISTRY, Paul R. START, Nisha ANANTHAKRISHNAN, Yawei LIANG, Jigneshkumar P. PATEL, Sairam AGRAHARAM, Liwei WANG
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Publication number: 20190326198Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Applicant: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Patent number: 10373893Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.Type: GrantFiled: June 30, 2017Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Publication number: 20190043778Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.Type: ApplicationFiled: December 26, 2015Publication date: February 7, 2019Inventors: Zhizhong TANG, Shinobu KOURAKATA, Kazuo OGATA, Paul R. START, Syadwad JIAN, William Nicholas LABANOK, Wei HU, Peng LI, Douglas R. YOUNG, Gregory S. CONSTABLE, John J. Beatty, Pardeep K. BHATTI, Luke J. GARNER, Aravindha R. ANTONISWAMY
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Publication number: 20190006264Abstract: An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Patent number: 9461014Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.Type: GrantFiled: April 14, 2015Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
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Publication number: 20150221609Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.Type: ApplicationFiled: April 14, 2015Publication date: August 6, 2015Applicant: Intel CorporationInventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
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Patent number: 9064971Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.Type: GrantFiled: December 20, 2012Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
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Patent number: 8866290Abstract: Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed.Type: GrantFiled: March 15, 2013Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Zhizhong Tang, Syadwad Jain, Paul R. Start
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Publication number: 20140264821Abstract: Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Zhizhong Tang, Syadwad Jain, Paul R. Start
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Publication number: 20140239479Abstract: A microelectronic package of the present description may include a microelectronic interposer having a first surface with an active surface of the at least one microelectronic device electrically attached to the microelectronic interposer first surface. A thermal interface material may be disposed on a back surface of the at least one microelectronic device. A heat spreader, having a first surface and an opposing second surface, may be in thermal contact by its first surface with the thermal interface material. A mold material may be disposed to encapsulate the microelectronic device, the thermal interface material, and the heat spreader, wherein the mold material abuts at least a portion of the microelectronic interposer first surface.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Inventor: Paul R Start
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Publication number: 20140175644Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
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Patent number: 8703536Abstract: An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.Type: GrantFiled: June 7, 2013Date of Patent: April 22, 2014Assignee: Intel CorporationInventors: Paul R. Start, Rahul N. Manepalli
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Publication number: 20140024176Abstract: Integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the INS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.Type: ApplicationFiled: June 7, 2013Publication date: January 23, 2014Inventors: Paul R. Start, Rahul N. Manepalli
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Patent number: 8508040Abstract: An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.Type: GrantFiled: December 1, 2010Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Paul R. Start, Rahul N. Manepalli