Patents by Inventor Paul R. Thayer

Paul R. Thayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Faster shift value calculation using modified carry-lookahead adder
    Patent number: 7444366
    Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce the value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: October 28, 2008
    Assignees: Hewlett-Packard Development Company, L.P., Intel Corporation
    Inventors: Paul R. Thayer, Sanjay Kumar
  • Faster shift value calculation using modified carry-lookahead adder
    Patent number: 7240085
    Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce a value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: July 3, 2007
    Assignees: Hewlett-Packard Development Company, L.P., Intel Corporation
    Inventors: Paul R. Thayer, Sanjay Kumar
  • Faster shift value calculation using modified carry-lookahead adder
    Publication number: 20040220991
    Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce the value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.
    Type: Application
    Filed: May 26, 2004
    Publication date: November 4, 2004
    Inventors: Paul R. Thayer, Sanjay Kumar
  • Faster shift value calculation using modified carry-lookahead adder
    Publication number: 20040068531
    Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce a value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.
    Type: Application
    Filed: July 7, 2003
    Publication date: April 8, 2004
    Inventors: Paul R. Thayer, Sanjay Kumar