Abstract: The present invention provides a computer implemented method and apparatus for determining the total capacitance of a primary interconnect line positioned between top and bottom ground planes. The primary interconnect line is positioned at a distance, H1, from the bottom ground plane and at a distance, H2, from the top ground plane. Preferred embodiments of the present invention include computer implemented processes for empirically determining the total capacitance of the primary interconnect line both with and without neighboring interconnect lines present. Core steps of the present invention include partitioning of a parameter representing fringe capacitance which is due to fringe electric fields induced between sidewalls of the primary interconnect line and the top and bottom ground planes. In the present invention, the fringing capacitance is partitioned into a top fringe capacitance, C.sub.

Abstract: A metal layer on an integrated circuit includes active signal lines and fill metal segments. The fill metal segments are polygons. Each fill metal segment at its narrowest has a width which is not greater than 1.25 times a design rule metal pitch for a technology used to fabricate the integrated circuit. In addition, each fill metal segment is separated from every other fill metal segment by spacing which is at least 0.7 times the design rule metal pitch for the technology used to fabricate the integrated circuit. Also, each fill metal segment is separated from every active signal line by spacing which is at least 0.5 times the design rule metal pitch for the technology used to fabricate the integrated circuit.