Patents by Inventor Paul Ravaux

Paul Ravaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5764894
    Abstract: A communication system for communicating with a network which includes a computer associated by means of a bus with a communication processor which is itself linked to a specific link of the network, the computer including a first operating system, and the processor including a second operating system, which handles the transmission of data from the bus to the network and vice versa. The communication system includes a telecommunication server associated with the first operating system, and a communication code which belongs to at least one open systems interconnection model associated with the second operating system, wherein the server provides the first operating system with access means to the various layers of the code, this code implementing the specific protocols of each layer, in order to enable transmission to the host or to the network.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: June 9, 1998
    Assignee: Bull S.A.
    Inventors: Gerard Boucher, Jean-Marc Gillon, Robert Perrin, Paul Ravaux
  • Patent number: 5561812
    Abstract: A data transmission system coupled between a computer bus (PBS) and a network (RE) includes a coupling device (GPU) linked to the bus and communicating by an interface with an adapter device (DEA) including a microprocessor (CPU2) connected to the network, an initial microprocessor (CPU1), and apparatus for transferring frames from the bus to the adapter device including a double port. The system is characterized by the fact that the interface is constituted by command files (F1 to F4) grouped in the memory, the second management processor handling software modules (ML1 , . . . ML10) independent of each other, to manage the emission and reception of specific frames from the network and communicating by means of letter boxes (BAL1, etc . . . ) included in the second processor and/or command files.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: October 1, 1996
    Assignee: Bull S.A.
    Inventors: Paul Ravaux, Pascal Urien
  • Patent number: 5455950
    Abstract: An operating system (GPOS) for universal device (GPU) for coupling a computer bus (PSB) to at least one specific link of a network (RN), the device includes a microprocessor (CPU) associated with at least one memory (SRAM) containing this system and means (MPC, B.sub.2, VRAM, B.sub.1, DMAC) for transferring frames from the computer bus to the link. The system is associated with a plurality of applications (A.sub.1 -A.sub.n) independent of one another, and includes a central core (NY) managing and organizing the work of each of the applications in real time, an applications manager (GA), which supervises and defines the state each of the applications must be in, and an intercommunications server (SA) for the applications, enabling each of them to request the services of another when that proves necessary. The core, the manager and the intercommunications server communicate between one another via system calls.
    Type: Grant
    Filed: July 15, 1992
    Date of Patent: October 3, 1995
    Assignee: Bull S.A.
    Inventors: Marc Vasseur, Paul Ravaux
  • Patent number: 5367646
    Abstract: An universal device (GPUI) for coupling a computer bus (PSB) to a controller (DEA) of a group of peripherals connected to one another by a specific link (FDDI) to which the controller is physically connected, includes a microprocessor (CPU) associated with a set of memories and an interface (IHAC, IHAD) for linkage with the controller (DEA) assuring the transfer of the data of the frames and of control blocks. The universal coupling device comprises a double-port random-access buffer memory (VRAM) connected by way of a first bus (B.sub.1) to the interface (IHAD) and by way of a second bus (B.sub.2) to the computer bus via a specific interface of the computer (MPC). Transfer of the data between the linking interface (IHAC, IHAD) and the double-port memory, on the one hand, and between the latter (VRAM) and the computer bus (PSB) on the other, is organized by a microprocessor (CPU), as is the conversion of control blocks used on the computer bus into those used in the link.
    Type: Grant
    Filed: July 15, 1992
    Date of Patent: November 22, 1994
    Assignee: Bull S.A.
    Inventors: Jacky Pardillos, Paul Ravaux