Abstract: A system and method for a beneficiary of Social Security payments or other retirement payments to access present value of future benefits to meet current financial and other objectives is provided. A financial institution is designated to be a direct depository and a disbursement agent for disbursing, at the direction of the beneficiary predetermined portions of retirement payments to a funding source or asset or service provider in exchange for access to capital or the acquisition of an asset or service by the beneficiary in an amount or having a value at least in part based on present value of a designated portion of future retirement payments. In the event of the premature termination of the beneficiary's participation in the program, the funding source or asset or service provider may seek reimbursement of a specified amount relating to the capital or asset or service it made available to the beneficiary, but not from subsequent retirement payments.

Abstract: A system and method for a beneficiary of Social Security payments or other retirement payments to access present value of future benefits to meet current financial and other objectives is provided. A financial institution is designated to be a direct depository and a disbursement agent for disbursing, at the direction of the beneficiary predetermined portions of retirement payments to a funding source or asset or service provider in exchange for access to capital or the acquisition of an asset or service by the beneficiary in an amount or having a value at least in part based on present value of a designated portion of future retirement payments. In the event of the premature termination of the beneficiary's participation in the program, the funding source or asset or service provider may seek reimbursement of a specified amount relating to the capital or asset or service it made available to the beneficiary, but not from subsequent retirement payments.

Abstract: An integrated circuit structure includes a substrate, diffused regions formed in the upper surface of the substrate, and thin and thick insulative regions, polycrystalline regions, and metallic interconnections selectively formed overlying selected areas of the substrate surface. An insulating passivation layer overlying the integrated circuit provides mechanical protection for the integrated circuit. Openings are selectively formed in the passivation layer overlying a portion of the integrated circuit at a position other than that of a bonding pad, and above one of the polycrystalline regions positioned over one of the thin insulating regions. The openings may be used to perform ion implantation to modify theelectrical characteristics, such as the threshold voltage, of the integrated circuit at those locations.

Abstract: A metal-oxide-semiconductor (MOS) structure and method for its fabrication wherein all contact hole locations are simultaneously photolithographically defined in the gate oxide layer and openings are etched at these locations prior to the deposition of polysilicon, which is then etched to form interconnections and contacts. The completed structure contains a thick oxide layer which forms an insulating dielectric which surrounds and is self-aligned with the contact holes and obviates the need for the commonly used intermediate layer of phosphosilicate glass. The width of the polysilicon contacts to sources and drains is less than the width of the active channel formed in a conventional n-channel silicon gate Metal-Oxide-Silicon field-effect transistor so that significant misalignment in the channel length direction between the opening in the gate oxide at a contact hole location and the polysilicon pattern will not cause failure of individual field effect transistors (FETs).

Abstract: A hermetic plastic package for a semiconductor integrated circuit chip includes a chip carrier provided with a plurality of conducting fingers that terminate at its underside. The carrier includes a pedestal onto which a semiconductor chip is bonded and wires are connected between the bonding pads on the chip and associated fingers on the carrier. A lid is placed over the carrier and is hermetically sealed with the chip inside the cavity of the carrier. The finger terminations on the underside of the carrier are connected to a plurality of leads which have inner portions that extend outward in a direction parallel to the underside of the carrier and end portions that are bent substantially perpendicular to the underside of the carrier configuration. The chip carrier and the inner portions of the leads that lie parallel to the underside of the chip carrier are encased in a plastic or epoxy compound.

Abstract: A method for fabricating an MOS integrated circuit having a refractory metal gate structure includes the formation of an insulating layer and a conductive refractory metal layer on a substrate, followed by the selective removal of portions of these layers to define the locations of source, drain, and other diffused regions. After the diffusion or implantation of the drain and source regions, using the refractory metal as a mask, the refractory metal, other than at the gate regions, is removed, and the portion of the underlying insulating layer that is thereby exposed is then etched away. An oxidizing step is performed to form a thick oxide region at those areas of the substrate not covered by the remaining portions of the refractory metal layer. Also disclosed is an MOS refractory metal gate MOS device fabricated by the method.

Abstract: A process for selectively modifying the electrical characteristics of selected MOS devices in an integrated circuit, such as in programming a read-only memory, at or near the final stage of circuit fabrication, includes the formation of a photoresist layer over the passivation layer of a nearly completed structure. Relatively narrow openings are formed in the photoresist at those locations at which it is desired to modify the underlying MOS devices, and wider openings are formed over the locations of bonding pads. Ion implantation is carried out through the narrow openings in the photoresist layer--the photoresist acting as an implantation barrier--to modify the underlying MOS devices. An oblique angle ion milling procedure is carried out in which the walls of the photoresist layer shield the passivation layer exposed by the narrow openings in the photoresist layer so as to remove the exposed portion of the passivation layer only over the bonding pad locations. The photoresist layer is subsequently removed.

Abstract: A method is disclosed for selectively modifying the electrical characteristics of MOS devices at a late stage in the fabrication process to form, for example, the "1" and "0" data locations of a ROM, or to form enhancement-and depletion-mode devices. In one embodiment of the method, in addition to forming openings in the passivation layer to define location of bonding pads, additional openings are formed in that layer at locations at which a data bit of one of the two levels is to be formed. Subsequently, an ion implantation is performed through the exposed underlying polysilicon gate structure to create an implantation layer at the channel regions of selected MOS devices, and thereby permanently alter the threshold voltages of these MOS devices. Other embodiments of the invention are disclosed in which ion implantation is performed through openings selectively formed in other layers, thereby to form implantation regions at selected locations to modify selected MOS devices at those locations.

Abstract: An MOS field effect transistor includes a substrate in which source and drain regions are formed. A thick silicon dioxide layer is selectively formed on the upper surface of the substrate, so that in the resulting structure, the junction depth associated with the source and drain regions is selectively greater at contact locations and at the portions of the source and drain regions that are in contact with the active channel.