Abstract: A method of operating a communication network having multiple stations, each able to transmit and receive data, so that the network can transmit a message from an originating station to a destination station via at least one opportunistically selected intermediate station. Stations wishing to transmit data transmit probe signals which are responded to by other stations, thereby to identify available stations. When a station has data to send, it transmits probe signals with Request to Send messages, identifying the data to be sent. When a station receives such data for onward transmission, it transmits its own probe signals with a Request to Send message and including identification information relating to the data. The Request to Send messages are received by other stations in the vicinity, so that they serve as an implied acknowledgement of the receipt of the data by the forwarding station without the need for sending explicit confirmation.

Abstract: Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

Abstract: Methods of creating a power distribution arrangement with tapered metal wires for a physical design are provided and described. In one embodiment, a method of creating a power distribution arrangement for a physical design of an integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. Each metal wire has a width. Furthermore, the metal wires are tapered such that the width is thicker in a core edge area of the physical design than in a core center area of the physical design. In other embodiments, a method of creating a power distribution arrangement for a physical design of a current integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. The metal wires are tapered using a routing congestion profile and/or a voltage drop profile of a prior physical design of a prior integrated circuit.

Abstract: Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

Abstract: Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.

Abstract: The invention relates to a method of operating a communication network, the network comprising a plurality of stations which are able to transmit data to and receive data from one another. The method comprises defining a first probing channel for the transmission of probe signals to other stations. Other stations which receive the first probe signals from a probing station indicate to the probing station their availability as destination or intermediate stations. A neighbor table comprising details of these other available stations is maintained at each station. Also, second probe signals are sent and received from stations in the neighbor table and a gradient table comprising data related to the cost of communicating with each neighbor station is maintained at each station, thereby to allow each station to select a predetermined number of intermediate stations for onward transmission of data from an originating station to a destination station at minimum cost.

Abstract: The invention relates to a method of operating a communication network, the network comprising a plurality of stations which are able to transmit data to and receive data from one another so that a message comprising a plurality of data packets is sent from an originating station to a destination station via at least one opportunistically selected intermediate station. The method makes use of probe signals transmitted from each station on a selected probing channel to which other stations respond to indicate their availability as destination or intermediate stations. A Request to Send message is sent, with a Clear to Send message returned by an available station. The station with data to send opportunistically selects an available station and the selected station uses a Packet Acknowledge message to confirm successful reception of the transmitted data packet. An End-to-End Acknowledge message is sent by the originating station, directly or indirectly, to confirm receipt of said data packets.

Abstract: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

Abstract: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

Abstract: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

Abstract: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit.

Abstract: A method and system for automatically generating low level design tool commands as dependency graphs from abstracted high level physical design stages. The novel system inputs names of blocks of a hierarchical integrated circuit. Each block name has associated with it certain variables, stages and conditional statements. The stages represent a set of linked physical design processes that are to be executed on the block. Stages can be dependent on other stages and therefore are executed in-order on the block depending on how they are linked in the input set. The system automatically generates, from the input set, a dependency graph for each block. The dependency graph includes a large volume of nodes with associated parameters and options. Each node includes one or more low level program commands (“tasks”) for directing a number of physical design tools, e.g., programs, to perform various functions with respect to the block. Each node can receive input and generate an output.

Abstract: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file and parsing the input file to identify elements within the netlist matching corresponding elements within a first library file. At least one element within the netlist is identified that does not have a corresponding element within the first library file. A modifiable element corresponding to the at least one element is stored within a second library file. A subsequent occurrence of the at least one element is matched to the modifiable element in the second library file. The parsing of the input file of the integrated circuit netlist is completed and a build of the integrated circuit netlist is then completed based on the parsed input file and specifications stored in the first or second library files.

Abstract: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file containing identifications of a plurality of blocks of cells of the integrated circuit netlist, each block representing circuit components to be realized in physical form. A view of the plurality blocks is presented to a user, the view provided by a computer display. Attach points are defined for each block. Connections for the blocks are defined by graphically linking the attach points of the respective blocks. The input file is updated in accordance with the defined connections.

Abstract: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing vertical and horizontal dimensions of an area of an integrated circuit netlist and accessing a grid for power and ground lines of the integrated circuit netlist. A view is presented of the grid to a user by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, wherein each block represents circuit components to be realized in physical form. The dimensions of the plurality of blocks to the grid such that the dimensions of the blocks align with the grid.

Abstract: A method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes the step of accessing vertical and horizontal dimensions of an area of an integrated circuit netlist. A grid for power and ground lines of the integrated circuit netlist is then accessed. A view of the grid is presented to a user, wherein the view is provided by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, with each block representing circuit components to be realized in physical form. The dimensions of the plurality of blocks are snapped to the grid such that the dimensions of the blocks align with the grid.

Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit, dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit.

Abstract: A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.

Abstract: A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.