Patents by Inventor Paul Ronald Stribley
Paul Ronald Stribley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947662Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.Type: GrantFiled: June 27, 2007Date of Patent: April 17, 2018Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, John Nigel Ellis
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Patent number: 9559170Abstract: A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.Type: GrantFiled: March 1, 2012Date of Patent: January 31, 2017Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 9524963Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.Type: GrantFiled: March 15, 2013Date of Patent: December 20, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 9331211Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.Type: GrantFiled: August 28, 2009Date of Patent: May 3, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, Soon Tat Kong
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Publication number: 20140264740Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 8729666Abstract: A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (42) and a second capacitor (44) that one connected in an anti-parallel manner. The insulating layer (18) of the first capacitor comprises silicon nitride and the insulating layer (16) of the second capacitor comprises silicon dioxide.Type: GrantFiled: September 23, 2009Date of Patent: May 20, 2014Assignee: X-Fab Semiconductor Foundries AGInventors: Paul Ronald Stribley, Soon Tat Kong, David John Verity
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Publication number: 20130228868Abstract: A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 8455955Abstract: An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.Type: GrantFiled: June 29, 2007Date of Patent: June 4, 2013Assignee: X-Fab Semiconductor Foundries AGInventors: Paul Ronald Stribley, John Nigel Ellis
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Patent number: 8378451Abstract: A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10?,20?,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10,10?) of the CMOS process as one plate and a thinner conductive layer (11,11?) as the second plate, with an insulating layer (20,20?) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor.Type: GrantFiled: July 18, 2008Date of Patent: February 19, 2013Assignee: X-FAB Semiconductor Foundries AGInventors: Paul Ronald Stribley, Mark Parsons, Graham Chapman
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Publication number: 20120211747Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.Type: ApplicationFiled: August 28, 2009Publication date: August 23, 2012Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, Soon Tat Kong
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Publication number: 20120211868Abstract: A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (42) and a second capacitor (44) that one connected in an anti-parallel manner.Type: ApplicationFiled: September 23, 2009Publication date: August 23, 2012Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, Soon Tat Kong, David John Verity
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Publication number: 20100252880Abstract: A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).Type: ApplicationFiled: July 18, 2008Publication date: October 7, 2010Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Publication number: 20100237465Abstract: A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10?,20?,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10,10?) of the CMOS process as one plate and a thinner conductive layer (11,11?) as the second plate, with an insulating layer (20,20?) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor.Type: ApplicationFiled: July 18, 2008Publication date: September 23, 2010Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, Mark Parsons, Graham Chapman
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Publication number: 20100059851Abstract: A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit.Type: ApplicationFiled: June 27, 2007Publication date: March 11, 2010Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: John Nigel Ellis, Paul Ronald Stribley, Jun Fu
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Publication number: 20090315119Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.Type: ApplicationFiled: June 27, 2007Publication date: December 24, 2009Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, John Nigel Ellis
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Publication number: 20090315080Abstract: An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.Type: ApplicationFiled: June 29, 2007Publication date: December 24, 2009Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, John Nigel Ellis
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Patent number: 6933551Abstract: An integrated circuit capacitor and an integrated circuit are provided. The integrated circuit capacitor includes at least first, second and third conducting plates. The first conducting plate is positioned between the second and third plates. A first dielectric layer is positioned between the first and third conducting plates. A second dielectric layer is positioned between the first and second conducting plates. An “overlap portion” of the second conducting plate extends beyond the edge of the first conducting plate and towards the third conducting plate. The capacitor is arranged so that the electrical breakdown voltage between the overlap portion and the third conducting plate is lower than the electrical breakdown voltage between the first and second conducting plates.Type: GrantFiled: April 4, 2003Date of Patent: August 23, 2005Assignee: Zarlink Semiconductor LimitedInventors: Paul Ronald Stribley, Gary Charles Day, Bo Goran Alestig
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Patent number: 6815264Abstract: A method of producing an antifuse, comprises the steps of: depositing a layer of undoped or lightly doped polysilicon on a layer of silicon dioxide on a semiconductor wafer; doping one region of the polysilicon P+; doping another region of the polysilicon N+, leaving an undoped or lightly doped region between the P+ and N+ regions; and forming electrical connections to the P+ and N+ regions.Type: GrantFiled: November 19, 2002Date of Patent: November 9, 2004Assignee: Zarlink Semiconductor LimitedInventors: Paul Ronald Stribley, John N Ellis, Ian G Daniels
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Publication number: 20030094671Abstract: A method of producing an antifuse, comprises the steps of:Type: ApplicationFiled: November 19, 2002Publication date: May 22, 2003Inventors: Paul Ronald Stribley, John N. Ellis, Ian G. Daniels