Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: In a data processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses, having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data, an arrangement for extending a range of addressable storage beyond the basic range allowed by the instruction codes. The processor is equipped to generate a long address, i.e., 30-bits, even though the instruction execution means can only generate a 23-bit address. When the processor goes into an alternate mode, the contents of a segment control register are prefixed onto the addresses generated within the processor when a certain class of instructions are executed.

Abstract: A receiver is disclosed which operates for synchronously receiving pulses of a serial stream without synchronizing the receiver clock to the clock at a transmitting site. Circuitry is provided for generating multiple delayed pulse signals in response to each incoming pulse and for sampling and maintaining a sequence of the most recent samples of the pulse signals. Decoding logic detects state transitions within the sequence, the location therein being indicative of the phase of the pulses relative to the clock signals. The decoding logic operates other circuitry for tracking the phase of the pulses as it drifts. The phase tracking circuitry enables the selection of ones of the samples which are synchronized, or in pulse durational phase, with the receiver clock for reconstructing the incoming pulse stream.