Abstract: A system and method for managing accesses to a memory are provided. A memory management unit (MMU) and a translation lookaside buffer (TLB) are used. The TLB stores addresses of pages which have been recently accessed. The MMU includes a virtual map of an MMU table which stores physical addresses of memory pages linked to logical addresses. A virtual map is stored in a linear address space and the MMU can update the addresses stored in the TLB in response to memory accesses made in the MMU table. The MMU table comprises at least first and second level table entries. The first level table entries store data for map logical addresses to the second level table entries. The second level table entries store data for map logical addresses to physical addresses in memory.

Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Abstract: A testing method and device for detecting the existence of “stuck-open”, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.

Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Abstract: A swept fan blade design for the low pressure compressor rotor or fan rotor stage of a ducted fan gas turbine engine has a leading edge swept forward near the hub up to a first radial height, then rearward up to second radial height and finally is swept forward again up to the blade tip. The aerodynamic effect is to produce a mid-height bias to the airflow enabling the tip region to be given increased twist and to possess increased resistance to foreign object damage. The design also provides a rear radial blade stacking axis to help reduce internal stresses due to centrifugal forces.

Abstract: A data processing management system for controlling the execution of multiple threads of processing instructions such as the instructions that are employed to process multimedia data. The management system includes a media control core, a number of data processing units and a multi-banked cache. For the processing instruction for each thread, the multimedia core identifies the data processing operation to be executed as well as the resources needed to execute that operation. The multimedia core then determines for each instruction if all the resources are available to execute the operation. For the operations for which all the resources are available, the multimedia core then determines which operation has the highest priority. The operation having the highest priority is then passed to one of the data processing units for execution. The data and addresses upon which the data processing units act are temporarily stored in the multi-banked cache. Data are written into the cache from multiple input ports.