Abstract: A method of adjusting a power density in a laser device including a VCSEL array providing an increased power density at a high wall-plug efficiency in that the lateral design parameters are appropriately selected on the basis of a relationship that has been established for a specified vertical design, a corresponding process technology and specified operating conditions. Thus, the total output power, the power density, and the efficiency may be optimized independently from other design criteria and application requirements by tuning only the lateral size of the individual VCSEL elements and the pitch of nearest neighbors of the elements within the array. Hence, for a lateral size of less than 30 ?m and a pitch of less than 80 ?m, a highly efficient VCSEL array can be provided with a high power density, thereby optimizing manufacturing costs for the output power per chip area.

Abstract: A method of adjusting a power density in a laser device including a VCSEL array providing an increased power density at a high wall-plug efficiency in that the lateral design parameters are appropriately selected on the basis of a relationship that has been established for a specified vertical design, a corresponding process technology and specified operating conditions. Thus, the total output power, the power density, and the efficiency may be optimized independently from other design criteria and application requirements by tuning only the lateral size of the individual VCSEL elements and the pitch of nearest neighbors of the elements within the array. Hence, for a lateral size of less than 30 ?m and a pitch of less than 80 ?m, a highly efficient VCSEL array can be provided with a high power density, thereby optimizing manufacturing costs for the output power per chip area.

Abstract: A laser device including a VCSEL array provides an increased power density at a high wall-plug efficiency in that the lateral design parameters are appropriately selected on the basis of a relationship that has been established for a specified vertical design, a corresponding process technology and specified operating conditions. Thus, the total output power, the power density, and the efficiency may be optimized independently from other design criteria and application requirements by tuning only the lateral size of the individual VCSEL elements and the pitch of nearest neighbors of the elements within the array. Hence, for a lateral size of less than 30 ?m and a pitch of less than 80 ?m, a highly efficient VCSEL array can be provided with a high power density, thereby optimizing manufacturing costs for the output power per chip area.

Abstract: The present invention provides a VCSEL device (100) and a method of fabricating the same, wherein two or more characteristic device dimensions (DM, DP) are correlated with each other so as to optimise single mode emission, while at the same time significantly providing an increased oxide aperture (DOX) compared to conventional devices. Thus, device lifetime and reliability are enhanced. The present invention may rely on well-established process techniques for VCSEL devices having an oxide aperture (DOX), wherein merely one additional mesa etch step is required.