Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

Abstract: A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.

Abstract: A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.

Abstract: A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is located above the transistor and traverses the memory in a direction perpendicular to the control gate.

Abstract: The present invention provides methods of fabricating floating gate transistors. One method includes forming laterally spaced source and drain regions to define a channel therebetween, forming a first floating gate portion above the channel region, the first floating gate portion extending in a general horizontal direction, forming spacers over the first floating gate portion to define an exposed region on the first floating gate portion, forming a contact coupled to the first floating gate portion at the exposed region, the contact extending vertically above the first portion, forming a second floating gate portion coupled to the contact, the second floating gate portion extending in a general vertical direction, and forming a control gate adjacent to the second portion.

Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.

Abstract: A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.

Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is located above the transistor and traverses the memory in a direction perpendicular to the control gate.

Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

Abstract: A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential.

Abstract: A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential.