Abstract: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.

Abstract: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.

Abstract: A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins.

Abstract: A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the memory device.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net.

Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

Abstract: A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net.

Abstract: A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller.

Abstract: A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the memory device.

Abstract: Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.

Abstract: A method of enabling triggering an oscilloscope includes placing a tip portion of a probe, electrically connected to the oscilloscope, on an electrical circuit, applying pressure to the probe tip, and establishing an electrical contact inside the probe as a result of pressure applied to the probe tip. The electrical contact closes an electrical circuit that triggers the oscilloscope.

Abstract: Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.