Patents by Inventor Paul S. Cheses

Paul S. Cheses has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interference testing
    Patent number: 10516439
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • INTERFERENCE TESTING
    Publication number: 20170359099
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Application
    Filed: August 1, 2017
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • Interference testing
    Patent number: 9722663
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • INTERFERENCE TESTING
    Publication number: 20150280781
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenien, James M. Shehadi