Patents by Inventor Paul S. Heckbert
Paul S. Heckbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9007389Abstract: Embodiments of the present invention are directed towards increasing texture filtering performance for texel components represented by more than 8 bits. As the number of bits per component increases, the number of texels that are processed each clock cycle decreases since more bits need to be processed to produce each filtered result. A filtered result may be accumulated over two or more iterations, with each iteration producing a portion of the filtered result. When only a portion of the components for each texel are used, the unused texel components are not processed. Elimination of unnecessary texel processing for unused texel components may improve texture filtering performance.Type: GrantFiled: June 21, 2007Date of Patent: April 14, 2015Assignee: NVIDIA CorporationInventor: Paul S. Heckbert
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Patent number: 8340423Abstract: Methods and systems for updating mosaics of digital source images are disclosed. According to one embodiment, a method for updating a mosaic of digital source images includes segmenting the mosaic to regions, generating a plurality of region-statistics where each region-statistics correspond to image characteristics of one region, organizing the plurality of region-statistics in a database, and updating the mosaic using at least one target region-statistics from the organized plurality of region-statistics. Updating the mosaic can include color correcting. The method for updating a mosaic of digital source images can also includes optimizing the organized plurality of region-statistics, wherein the optimizing is based on one or more reference region-statistics from the organized plurality of region-statistics.Type: GrantFiled: September 29, 2009Date of Patent: December 25, 2012Assignee: Google Inc.Inventors: Stephen D. Zelinka, Paul S. Heckbert
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Patent number: 8031204Abstract: Systems and methods used for bilinear texture filtering may also be used to perform font filtering. Font data stored as a texture is read from memory in blocks that are coarsely aligned. Font alignment units may be used to provide a finely aligned region of the font data within a font filter footprint. The finely aligned region is then filtered using bilinear filtering to produce font coverage information representing a grayscale value for a pixel. Using existing bilinear filtering engines in conjunction with font alignment and sample units reduces the need for having a specific engine to perform each of the font filtering operations, possibly saving die area in a graphics system.Type: GrantFiled: June 21, 2007Date of Patent: October 4, 2011Assignee: NVIDIA CorporationInventors: Paul S. Heckbert, John W. Berendsen
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Patent number: 7982745Abstract: Trilinear optimization is a technique to reduce the number of texture samples used to determine a texture value associated with a graphics fragment. Bilinear interpolations replace some trilinear interpolations, thereby reducing the number of texture samples read and simplifying the filter computation. A programmable trilinear slope is used to control replacement of a trilinear computation with a bilinear computation, permitting a user to determine a balance between improved texture map performance and texture filtering quality.Type: GrantFiled: December 13, 2007Date of Patent: July 19, 2011Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert
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Patent number: 7884831Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.Type: GrantFiled: January 19, 2010Date of Patent: February 8, 2011Assignee: NVIDIA CorporationInventors: Alexander L. Minkin, Joel J. McCormack, Paul S. Heckbert, Michael J. M. Toksvig, Luke Y. Chang, Karim Abdalla, Bo Hong, John W. Berendsen, Walter Donavan, Emmett M. Kilgariff
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Patent number: 7852347Abstract: The current invention involves new systems and methods for increasing texture filtering performance by reorganizing a texture sampling order used to read and filter texels when anisotropic filtering is used. Texel read performance is improved for anisotropic filtering by reorganizing texel reads when a texel cache is used. The texel reads are paired based on a major axis alignment in pixel space. The paired texel reads for a pixel footprint may also be ordered to improve texel coherency, thereby improving a texture cache hit rate.Type: GrantFiled: June 21, 2007Date of Patent: December 14, 2010Assignee: NVIDIA CorporationInventor: Paul S. Heckbert
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Patent number: 7773092Abstract: The current invention involves new systems and methods for increasing texture filtering performance based on pixel coverage. When half of the pixels in a 2×2 pixel quad are not covered, texel coordinates for the uncovered pixels are not output. Therefore, the texels for the uncovered pixels are not read or processed, allowing the texel filtering processing throughput to be used to produce filtered results for covered pixels. This optimization is particularly useful when anisotropic filtering is used since the number of texels needed to produce a filtered result for a pixel increases as the anisotropic ratio increases. Elimination of unnecessary texel processing for uncovered pixels may improve texture filtering performance.Type: GrantFiled: June 21, 2007Date of Patent: August 10, 2010Assignee: NVIDIA CorporationInventor: Paul S. Heckbert
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Publication number: 20100118043Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: NVIDIA CorporationInventors: Alexander L. Minkin, Joel J. McCormack, Paul S. Heckbert, Michael J.M. Toksvig, Luke Y. Chang, Karim Abdalla, Bo Hong, John W. Berendsen, Walter Donavan, Emmett M. Kilgariff
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Patent number: 7649538Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.Type: GrantFiled: November 3, 2006Date of Patent: January 19, 2010Assignee: NVIDIA CorporationInventors: Alexander L. Minkin, Joel J. McCormack, Paul S. Heckbert, Michael J. M. Toksvig, Luke Y. Chang, Karim Abdalla, Bo Hong, John W. Berendsen, Walter Donovan, Emmett M. Kilgariff
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Patent number: 7595806Abstract: A method for implementing LOD (level of detail) filtering in a cube mapping application. The method includes accessing a first sample and a second sample for a cube map. A cube map path is computed between the first sample and the second sample. A distance is computed between the first sample and the second sample, wherein the distance is measured using the cube map path. LOD filtering is then implemented by using the distance between the first sample and the second sample.Type: GrantFiled: August 3, 2004Date of Patent: September 29, 2009Assignee: NVIDIA CorporationInventors: Michael J. M. Toksvig, William P. Newhall, Jr., Paul S. Heckbert
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Patent number: 7586496Abstract: Shortening a footprint is a technique to reduce the number of texture samples anisotropically filtered to determine a texture value associated with a graphics fragment. Reducing the number of texture samples anisotropically filtered reduces the number of texture samples read and simplifies the filter computation. Programmable knobs are used to shorten the footprint of a pixel in texture space thereby reducing the number of texture samples used during anisotropic filtering. These knobs permit a user to determine a balance between improved texture map performance and anisotropic texture filtering quality.Type: GrantFiled: May 8, 2007Date of Patent: September 8, 2009Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert
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Patent number: 7369136Abstract: A system and method for computing anisotropic texture mapping parameters by using approximation techniques reduces the complexity of the calculations needed to perform high quality anisotropic texture filtering. Anisotropic texture mapping parameters that are approximated may be computed using dedicated processing units within a graphics processor, thereby improving anisotropic texture mapping performance. Specifically, the major axis and minor axis of anisotropy are determined and their respective lengths are calculated using approximations. Other anisotropic texture mapping parameters, such as a level of detail for selecting a particular level are computed based on the calculated lengths of the major and minor axes.Type: GrantFiled: December 17, 2004Date of Patent: May 6, 2008Assignee: NVIDIA CorporationInventors: Paul S. Heckbert, Stuart F. Oberman
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Patent number: 7221371Abstract: Shortening a footprint is a technique to reduce the number of texture samples anisotropically filtered to determine a texture value associated with a graphics fragment. Reducing the number of texture samples anisotropically filtered reduces the number of texture samples read and simplifies the filter computation. Programmable knobs are used to shorten the footprint of a pixel in texture space thereby reducing the number of texture samples used during anisotropic filtering. These knobs permit a user to determine a balance between improved texture map performance and anisotropic texture filtering quality.Type: GrantFiled: March 30, 2004Date of Patent: May 22, 2007Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert
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Patent number: 7193627Abstract: Trilinear optimization is a technique to reduce the number of texture samples used to determine a texture value associated with a graphics fragment. Bilinear interpolations replace some trilinear interpolations, thereby reducing the number of texture samples read and simplifying the filter computation. A programmable trilinear slope is used to control replacement of a trilinear computation with a bilinear computation, permitting a user to determine a balance between improved texture map performance and texture filtering quality.Type: GrantFiled: December 5, 2005Date of Patent: March 20, 2007Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert
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Patent number: 7167183Abstract: The current invention involves new systems and methods for reorganizing a texture sampling order that is used to read texels from a texel cache. When anisotropic filtering is used to process the texels read from the texel cache, the texels are read in an order based on a major axis alignment. Reorganizing texture sampling order to use the order based on the major axis alignment results in improved texel cache locality, thereby improving texel cache performance.Type: GrantFiled: October 14, 2004Date of Patent: January 23, 2007Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Anders M. Kugler, William P. Newhall, Jr., Paul S. Heckbert
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Patent number: 6995767Abstract: Trilinear optimization is a technique to reduce the number of texture samples used to determine a texture value associated with a graphics fragment. Bilinear interpolations replace some trilinear interpolations, thereby reducing the number of texture samples read and simplifying the filter computation. A programmable trilinear slope is used to control replacement of a trilinear computation with a bilinear computation, permitting a user to determine a balance between improved texture map performance and texture filtering quality.Type: GrantFiled: July 31, 2003Date of Patent: February 7, 2006Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert