Patents by Inventor Paul S. Ho

Paul S. Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11103460
    Abstract: Embodiments of the present disclosure include devices, and methods of making such devices, for delivery of one or more active agents with short or long zero-order release kinetics. Embodiments also include implantable or injectable drug delivery systems capable of controlled release over long periods of time for therapeutic agents.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 31, 2021
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Paul S. Ho, Junjun Liu, Tengfei Jiang, Salomon A. Stavchansky
  • Patent number: 10727165
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Tengfei Jiang
  • Publication number: 20190139864
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Paul S. Ho, Tengfei Jiang
  • Publication number: 20190038565
    Abstract: Embodiments of the present disclosure include devices, and methods of making such devices, for delivery of one or more active agents with short or long zero-order release kinetics. Embodiments also include implantable or injectable drug delivery systems capable of controlled release over long periods of time for therapeutic agents.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 7, 2019
    Inventors: Paul S. HO, Junjun LIU, Tengfei JIANG, Salomon A. STAVCHANSKY
  • Patent number: 10170399
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: January 1, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Tengfei Jiang
  • Publication number: 20180042549
    Abstract: A method of making an injectable or implantable active agent delivery device capable of delivering a diagnostic, therapeutic, and/or prophylactic agent to a desired targeted site having orifice(s) on the surface is disclosed herein providing unidirectional release of the agent at a controlled desirable rate. The agent may include, but is not limited to, drugs, proteins, peptides, biomarkers, bioanalytes, and/or genetic material. The technology of the invention is based on parallel processing to fabricate micro-holes on tubes employing photo-lithography and reactive ion etching techniques and also incorporates a simple molding method to form the micro-holes on flexible polymer tubes, including bio-degradable tubes. The parallel processing method of the instant invention is fast, economical and well suited for mass production. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time.
    Type: Application
    Filed: July 27, 2017
    Publication date: February 15, 2018
    Inventors: Paul S. HO, Salomon STAVCHANSKY, Phillip BOWMAN, Zhiquan LUO, Zhuojie WU, Ashish RASTOGI
  • Publication number: 20180012824
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: Paul S. Ho, Tengfei Jiang
  • Patent number: 9403675
    Abstract: The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate. The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 2, 2016
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Paul S. Ho, Zhuojie Wu
  • Publication number: 20160172457
    Abstract: The present disclosure relates to a method of fabricating a silicon nanowire having a width of 100 nm or less, especially 50 nm or less, by depositing a metal film on a silicon-containing layer, treating the metal film using a wet process to produce an interconnected metal network having gaps on the silicon-containing layer, and etching the silicon-containing layer with a metal-assisted etching process to form a silicon nanowire having a width of 100 nm or less, especially 50 nm or less.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 16, 2016
    Inventors: Paul S. Ho, Zhuojie Wu
  • Publication number: 20150208982
    Abstract: A method of making an injectable or implantable active agent delivery device capable of delivering a diagnostic, therapeutic, and/or prophylactic agent to a desired targeted site having orifice(s) on the surface is disclosed herein providing unidirectional release of the agent at a controlled desirable rate. The agent may include, but is not limited to, drugs, proteins, peptides, biomarkers, bioanalytes, and/or genetic material. The technology of the invention is based on parallel processing to fabricate micro-holes on tubes employing photo-lithography and reactive ion etching techniques and also incorporates a simple molding method to form the micro-holes on flexible polymer tubes, including bio-degradable tubes. The parallel processing method of the instant invention is fast, economical and well suited for mass production. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time.
    Type: Application
    Filed: February 3, 2015
    Publication date: July 30, 2015
    Inventors: Paul S. HO, Salomon STAVCHANSKY, Phillip BOWMAN, Zhiquan LUO, Zhuojie WU, Ashish RASTOGI
  • Patent number: 9005649
    Abstract: A method of making an injectable or implantable active agent delivery device capable of delivering a diagnostic, therapeutic, and/or prophylactic agent to a desired targeted site having orifice(s) on the surface is disclosed herein providing unidirectional release of the agent at a controlled desirable rate. The agent may include, but is not limited to, drugs, proteins, peptides, biomarkers, bioanalytes, and/or genetic material. The technology of the invention is based on parallel processing to fabricate micro-holes on tubes employing photo-lithography and reactive ion etching techniques and also incorporates a simple molding method to form the micro-holes on flexible polymer tubes, including bio-degradable tubes. The parallel processing method of the instant invention is fast, economical and well suited for mass production. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 14, 2015
    Assignee: Board of Regents, the University of Texas System
    Inventors: Paul S. Ho, Salomon Stavchansky, Phillip Bowman, Zhiquan Luo, Zhuojie Wu, Ashish Rastogi
  • Publication number: 20150054135
    Abstract: The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate. The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 26, 2015
    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Paul S. Ho, Zhuojie Wu
  • Publication number: 20120177716
    Abstract: A method of making an injectable or implantable active agent delivery device capable of delivering a diagnostic, therapeutic, and/or prophylactic agent to a desired targeted site having orifice(s) on the surface is disclosed herein providing unidirectional release of the agent at a controlled desirable rate. The agent may include, but is not limited to, drugs, proteins, peptides, biomarkers, bioanalytes, and/or genetic material. The technology of the invention is based on parallel processing to fabricate micro-holes on tubes employing photo-lithography and reactive ion etching techniques and also incorporates a simple molding method to form the micro-holes on flexible polymer tubes, including bio-degradable tubes. The parallel processing method of the instant invention is fast, economical and well suited for mass production. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time.
    Type: Application
    Filed: July 14, 2010
    Publication date: July 12, 2012
    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Paul S. Ho, Salomon Stavchansky, Phillip Bowman, Zhiquan Luo, Zhuojie Wu, Ashish Rastogi
  • Publication number: 20120130300
    Abstract: An injectable or implantable medical device having orifice(s) on the surface that release an active agent with zero-order release kinetics is described herein. The device is a hollow matrix of any size or shape, which can be made from both metal and non-metal surfaces. The device comprises of a reservoir capable of releasing at least one therapeutic, diagnostic, or prophylactic agent via the orifices to the desired anatomical site. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time. The composition provides zero-order kinetics, in part, because the diffusion rate of the drug from the device is slow which enables sink conditions. Hence, no back transfer or build up of drug occurs at anytime. Polymers are not required for controlled release.
    Type: Application
    Filed: July 14, 2010
    Publication date: May 24, 2012
    Applicant: Board of Regents, The Univerity of Texas System
    Inventors: Salomon S. Stavchansky, Phillip Bowman, Paul S. Ho, Ashish Rastogi, Zhiquan Luo, Zhuoijie Wu
  • Publication number: 20100117764
    Abstract: The selective growth of vertically aligned, highly dense carbon nanotube (CNT) arrays using a thermal catalytic chemical vapor deposition (CCVD) method via selection of the supporting layer where the thin catalyst layer is deposited on. A thin iron (Fe) catalyst deposited on a supporting layer of tantalum (Ta) yielded CCVD growth of the vertical dense CNT arrays. Cross-sectional transmission electron microscopy revealed a Vollmer-Weber mode of Fe island growth on Ta, with a small contact angle of the islands controlled by the relative surface energies of the supporting layer, the catalyst and their interface. The as-formed Fe island morphology promoted surface diffusion of carbon atoms seeding the growth of the CNTs from the catalyst surface.
    Type: Application
    Filed: April 17, 2006
    Publication date: May 13, 2010
    Inventors: Yunyu Wang, Paul S. Ho, Li Shi, Zhen Yao
  • Patent number: 7078817
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: July 18, 2006
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Patent number: 6919639
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 19, 2005
    Assignee: The Board of Regents, the University of Texas System
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Publication number: 20040070078
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Publication number: 20020017906
    Abstract: A test structure and a method for detecting early failures in a large ensemble of semiconductor elements, particularly applicable to on-chip interconnects, is provided. A novel approach to gain information about the statistical behavior of several thousand interconnects and to investigate possible deviations from perfect lognormal statistics is presented. A test structure having a Wheatstone Bridge arrangement and arrays of several hundred interconnects may be used to prove that failure data does not deviate from lognormal behavior down to a cumulative failure rate of approximately one out of 20,000. Typical test structure sizes may, therefore, be extended far beyond standard test procedures to gain information about the statistical behavior of failure mechanisms and to verify the validity of the assumption that failure mechanisms follow lognormal statistical behavior.
    Type: Application
    Filed: April 17, 2001
    Publication date: February 14, 2002
    Inventors: Paul S. Ho, Martin Gall
  • Patent number: 4886681
    Abstract: A technique is described for improving metal-organic substrate adhesion and for reducing stress between the metal film and the substrate. Low energy reactive ions, electrons, or photons are incident upon the substrate to alter the surface chemistry of the substrate to a depth of from about 10 angstroms to a few hundred angstroms. The energy of the incident reactive ions and electrons is about 50-2000 eV, while the energy of the incident photons is about 0.2-500 eV. Irradiation of the substrate can occur prior to or during metal deposition. For simultaneous metal deposition/particle irradiation, the arrival rates of the metal atoms and the substrate treatment particles are within a few order of magnitude of one another. Room temperatures or elevated temperatures are suitable.
    Type: Grant
    Filed: December 6, 1988
    Date of Patent: December 12, 1989
    Assignee: International Business Machines Corporation
    Inventors: Joachim G. Clabes, Peter O. Hahn, Paul S. Ho, Haralambos Lefakis, Gary W. Rubloff