Abstract: An enhanced arbitration and control subsystem for a self-refreshing DRAM has a normal mode of operation and a test mode of operation in which an internal refresh cycle is automatically performed prior to each external access cycle. A first gate is opened in a normal mode of operation to enable internal refresh cycles upon receipt of an internal refresh request signal. The first gate is closed in a test mode to disable any internal refresh requests. A second gate is opened in the test mode of operation to provide a path for an external access request signal to first trigger initiation of an internal refresh cycle prior to an external access cycle. The second gate is closed in a normal mode of operation to allow normal arbitration between internal refresh request signals and external RAS request signals.

Abstract: A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh request control signal to initiate an internal refresh cycle. A refresh-request storage element is reset upon initiation of an internal refresh cycle. A refresh miss detector provides an output pulse when the refresh request signal is received concurrent with the refresh request storage element being set. Provision is made to read out the count, and to reset the count. By reading out the count an indication is obtained of how many refresh requests were missed, and by using arbitrary input patterns the robustness of the self-refreshing DRAM is improved.

Abstract: Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

Abstract: An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a drain boost capacitor and to a drain precharge circuit. The gate boost capacitor is precharged from the common VCC voltage. The second terminal of the precharged gate boost capacitor is connected to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC. The drain of the NMOS pass transistor has a similar boost capacitor and precharge configuration. Another embodiment further includes an additional gate preboost capacitor and a gate preboost precharge circuit for boosting the gate voltage to 3 VCC to more efficiently drive the NMOS pass transistor.

Abstract: Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

Abstract: A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial access request. When access to the memory begins in a RAS cycle, this first request latch is reset. When a RAS cycle is currently underway, a second request-queuing latch is set in response to a new, second access request that occurs. Whenever a RAS cycle is completed, if the second queuing latch is set, a new RAS cycle is initiated and both the first and the second latches are reset. Any subsequent new access request may then be queued if the subsequent new access request arrives prior to completion of the current second access cycle.