Patents by Inventor Paul S. McLaughlin
Paul S. McLaughlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956339Abstract: A process control system (PCS) includes a cable connection including physical cables including a first cable for connecting between a process controller and an I/O access device, and an independent second cable for connecting the process controller and a second node being the I/O access device or another device. The I/O access device is for coupling to I/O module(s) to receive an output of the I/O access device. An output of the I/O module is coupled to a field device coupled to processing equipment. The process controller and I/O access device each include a processor and memory that implement send and receive logic for communicating using any of multiple redundancy protocols including a first and a second redundant protocol. The cable connection is for supporting simultaneously communicating between the process controller and the second node utilizing both the first redundant protocol and the second redundant protocol.Type: GrantFiled: December 31, 2020Date of Patent: April 9, 2024Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Harshal S. Haridas, Joseph Pradeep Felix, Jay William Gustin, Paul Francis Mclaughlin, Jason Thomas Urso
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Patent number: 10840174Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.Type: GrantFiled: April 12, 2017Date of Patent: November 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Shawn P. Fetterolf, Jin-Ping Han, Christian Lavoie, Paul S. McLaughlin, Ahmet S. Ozcan, Roger A. Quon
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Patent number: 10191108Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.Type: GrantFiled: November 19, 2015Date of Patent: January 29, 2019Assignee: Globalfoundries Inc.Inventors: Gregory G. Freeman, Siyuranga Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott, Scott Taylor, Gregory Uhlmann, James D. Warnock
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Publication number: 20180300599Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: SHAWN P. FETTEROLF, JIN-PING HAN, CHRISTIAN LAVOIE, PAUL S. MCLAUGHLIN, AHMET S. OZCAN, ROGER A. QUON
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Patent number: 9759766Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.Type: GrantFiled: July 20, 2016Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Baozhen Li, Paul S. McLaughlin
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Publication number: 20170176514Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.Type: ApplicationFiled: July 20, 2016Publication date: June 22, 2017Inventors: GRISELDA BONILLA, ELBERT E. HUANG, CHAO-KUN HU, BAOZHEN LI, PAUL S. MCLAUGHLIN
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Publication number: 20170146592Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.Type: ApplicationFiled: November 19, 2015Publication date: May 25, 2017Inventors: Gregory G. Freeman, Siyuranga Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott, Scott Taylor, Gregory Uhlmann, James D. Warnock
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Patent number: 9472477Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.Type: GrantFiled: December 17, 2015Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Baozhen Li, Paul S. McLaughlin
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Patent number: 9443776Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.Type: GrantFiled: June 3, 2015Date of Patent: September 13, 2016Assignee: GlobalFoundries, Inc.Inventors: Ronald G. Filippi, Jason P. Gill, Vincent J. McGahay, Paul S. McLaughlin, Conal E. Murray, Hazara S. Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Publication number: 20150262899Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.Type: ApplicationFiled: June 3, 2015Publication date: September 17, 2015Inventors: RONALD G. FILIPPI, JASON P. GILL, VINCENT J. MCGAHAY, PAUL S. MCLAUGHLIN, CONAL E. MURRAY, HAZARA S. RATHORE, THOMAS M. SHAW, PING-CHUAN WANG
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Patent number: 8922022Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.Type: GrantFiled: January 23, 2012Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Baozhen Li, Paul S. McLaughlin, Timothy D. Sullivan
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Patent number: 8726201Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.Type: GrantFiled: May 14, 2010Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Peter A. Habitz, Baozhen Li, Paul S. McLaughlin, Dileep N. Netrabile
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Publication number: 20120119366Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Baozhen Li, Paul S. McLaughlin, Timothy D. Sullivan
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Patent number: 8114768Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.Type: GrantFiled: December 29, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Baozhen Li, Paul S. McLaughlin, Timothy D. Sullivan
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Publication number: 20110283249Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeanne P. BICKFORD, Peter A. HABITZ, Baozhen LI, Paul S. MCLAUGHLIN, Dileep N. NETRABILE
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Patent number: 8053257Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.Type: GrantFiled: April 2, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Robert D. Edwards, Lawrence A. Clevenger, Andrew P. Cowley, Chih-Chao Yang, Conrad A. Barile
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Patent number: 7968456Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.Type: GrantFiled: May 20, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Paul S. McLaughlin, Sujatha Sankaran, Theodorus E. Standaert
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Publication number: 20100164116Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Baozhen Li, Paul S. McLaughlin, Timothy D. Sullivan
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Patent number: 7701035Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).Type: GrantFiled: November 30, 2005Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Erik L. Hedberg, Dae-Young Jung, Paul S. McLaughlin, Christopher D. Muzzy, Norman J. Rohrer, Jean E. Wynne
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Patent number: 7692439Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.Type: GrantFiled: May 22, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang