Abstract: An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.

Abstract: An apparatus and method are provided for describing the interaction between event monitoring subsystems. A plurality of interactively-connected event monitoring subsystems in a computing system are configured. Events are collected by a first event monitoring subsystem of the plurality of event monitoring subsystems. Additional event information regarding one or more additional events are collected by the one or more second event monitoring systems. This additional information is received at the first event monitoring subsystem from one or more second event monitoring subsystems. An action is also triggered by the first event monitoring subsystem. The action is based on one or both of the collected performance events and the additional performance event information.

Abstract: An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.

Abstract: A first queue receives transactions from a transaction source in first-in/first-out (FIFO) order regardless of priority. A second queue receives lower priority transactions from the first queue as compared to the higher priority transactions remaining in the first queue. A priority check module controls the forwarding schedule of transactions from the first and second queues in accordance with the associated priorities of the stored transactions. Should an address conflict arise between transactions in the first and second queues, the priority check module stalls forwarding from the first queue while promoting forwarding from the second queue during the conflict condition.

Abstract: A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.

Abstract: A system, apparatus and method enabling common memory pool tests to be conducted in a multiprocessing system by using substantially the same system components that are used during a normal mode of operation. Under normal mode of operation, a data cache interface facilitates data transfer between processors of a multiprocessor system and the common memory pool. In test mode of operation, an integrated data cache exerciser assumes control of the data cache interface to facilitate test data write and read operations to/from the common memory pool. Test data may be generated from data queues within the multiprocessing system that are also operational during normal mode of operation. Alternatively, the test data may be generated from the address used to access the common memory pool.

Abstract: A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.

Abstract: A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalidation can occur from system bus SNOOPs. In addition, level one and level two cache memory misses result in loading and recording of the requested data into both level one and level two cache memories. Furthermore, a level two cache memory parity error results in invalidation of the corresponding level one cache memory data.