Patents by Inventor Paul Schram

Paul Schram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase locked loop with simultaneous locking to low and high frequency clocks
    Patent number: 8907706
    Abstract: A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: December 9, 2014
    Assignee: Microsemi Semiconductor ULC
    Inventors: Krste Mitric, Paul Schram, Tanmay Zargar, David Colby, Cathy Zhang, Robertus van der Valk
  • PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS
    Publication number: 20140320181
    Abstract: A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 30, 2014
    Applicant: Microsemi Semiconductor ULC
    Inventors: Krste Mitric, Paul Schram, Tanmay Zargar, David Colby, Cathy Zhang, Robertus Van der Valk