Abstract: Described is an abradable component for a gas turbine engine that includes a base having an outboard side which receives a supply of cooling air in use and an inboard side with a plurality of walls thereon. The walls intersect one another to define an abradable network of open faced cells on a gas washed surface thereof, and at least one of the walls includes one or more through-holes for providing a flow of cooling air from the outboard side to the gas washed surface of the abradable network of open faced cells, when in use.

Abstract: Described is an abradable component for a gas turbine engine, comprising: a base having an outboard side which receives a supply of cooling air in use and a plurality of walls on an inboard side thereof, the walls adjoining one another to provide an abradable network of open faced cells at a gas washed surface thereof; wherein at least one wall includes one or more through-holes for providing a flow of cooling air from the outboard side to the gas washed surface of the abradable network of open faced cells, when in use.

Abstract: Product compositions, product walls, and molding processes are described. According to one aspect, a product composition includes a polyester layer and an N-polymer layer coupled to the polyester layer.

Abstract: A nozzle guide vane for a gas turbine comprises at least one aerofoil having a leading edge section provided with at least one internal cavity for conveying cooling fluid through the said leading edge section, and a plate like wall section extending from the leading edge section to provide a continuous surface between the aerofoil leading edge section and the aerofoil trailing edge on the suction side of the aerofoil.

Abstract: A bus analyzer system comprises an input buffers module, a data memory module, a control detection module, a link request registers module, and a computer interface. The input buffers module is configured to receive data signals from a plurality of serial data, control, and clock lines at an interface between a physical layer and a link layer of an IEEE-1394 bus device. The computer interface is configured for operative communication with a computer that stores application software having algorithms for carrying out instructions for data interleaving, data formatting, error detection, time tracking, and display. The bus analyzer system allows a user to view all activity at the interface between the link layer and the physical layer within any IEEE-1394 bus device. The bus analyzer system automates the process of capturing each of the high speed serial data or control streams, and reconstructs, displays, and time-stamps the properly formatted 1394 transaction, data, or command signals.

Abstract: Embodiments of the present invention include a frequency generator comprising a feedback loop with a transmission line integrated on a single integrated circuit. In one embodiment, a frequency generator comprises a phase detector and a voltage controlled oscillator coupled in series, and a transmission line having an input coupled to an output of the voltage controlled oscillator, the transmission line providing a time delay between the transmission line input and output, wherein the phase detector includes an input coupled to the transmission line output and another input coupled to the transmission line input. The phase detector, voltage controlled oscillator and transmission line are advantageously integrated on a single integrated circuit.

Abstract: Embodiments of the present invention reduce static phase offset in timing loops. In one embodiment, the present invention includes a timing loop comprising first and second phase detectors, wherein during a first time period, the first phase detector is coupled in a closed timing loop and the second phase detector is decoupled from the closed timing loop and calibrated, and during a second time period, the second phase detector is coupled in a closed timing loop and the first phase detector is decoupled from the closed timing loop and calibrated.

Abstract: Embodiments of the present invention include a controlled delay line circuit comprising a feedback loop including an integrated transmission line, wherein the integrated transmission line is used as a timing reference for the feedback loop and wherein the feedback loop and the transmission line are integrated on a single integrated circuit. The feedback loop may be a Delay Locked Loop, for example.

Abstract: Embodiments of the present invention include an integrated circuit comprising an integrated transmission line, wherein the integrated transmission line is used as a timing reference for a feedback loop and wherein the feedback loop and the transmission line are integrated on a single integrated circuit. The feedback loop and transmission line may be used as a frequency generator or controlled delay, for example. In another embodiment, the present invention includes a timing loop with first and second commutating phase detectors.