Abstract: This application discloses a system implementing tools and mechanisms to selectively load design data for logical equivalency check. The tools and mechanisms can identify a hierarchy of modules in a circuit design, perform a depth-first search of the hierarchy of modules starting with a root module to identify a subset of modules to parse, and selectively parse the subset of the modules in the circuit design. The tools and mechanisms can utilize the parsed subset of the modules to determine logical equivalence of the circuit design with at least another circuit design.

Abstract: This application discloses a system implementing tools and mechanisms to selectively load design data for logical equivalency check. The tools and mechanisms can identify a hierarchy of modules in a circuit design, perform a depth-first search of the hierarchy of modules starting with a root module to identify a subset of modules to parse, and selectively parse the subset of the modules in the circuit design. The tools and mechanisms can utilize the parsed subset of the modules to determine logical equivalence of the circuit design with at least another circuit design.

Abstract: Method and apparatus estimates fault coverage of a set of test vectors to be applied to a circuit containing sequential elements. The apparatus permits sequential elements to be represented as functional blocks rather than combinational circuits with feedback. This is accomplished by taking into account the external state of the sequential element during circuit simulation. The apparatus also takes into account high impedance as possible inputs and outputs.