Abstract: Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.

Abstract: A system and method are provided for temporally analyzing serial input data. The method comprises: establishing three thresholds; distinguishing present (first) high probability one bit value estimates; distinguishing present high probability zero bit value estimates; and, using a temporal analysis of bit values to distinguish indefinite present bit value estimates. Using a temporal analysis of bit values includes: distinguishing a present bit estimate below first threshold and above the third threshold as a zero if both the past (second) and the future (third) bits are one values and otherwise as a one; and, distinguishing a present bit value estimate above the second threshold and below the third threshold as a one if both the past and future bits are a zero value and otherwise as a zero.

Abstract: A system and method are provided for selecting an optimal threshold detection level for a single serial data input receiver. The method comprises: receiving a serial data stream of pseudorandom binary information; using a plurality of threshold detection levels, estimating bit values; comparing the differences between estimated bit values; and, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values. In some aspects, comparing the differences between estimated bit values includes: counting a first number of differences between the first and third thresholds; counting a second number of differences between the second and third thresholds; and, adjusting the first and second thresholds until the first number equals the second number.

Abstract: A system and method are provided for selecting an optimal threshold detection level for a single serial data input receiver. The method comprises: receiving a serial data stream of pseudorandom binary information; using a plurality of threshold detection levels, estimating bit values; comparing the differences between estimated bit values; and, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values. In some aspects, comparing the differences between estimated bit values includes: counting a first number of differences between the first and third thresholds; counting a second number of differences between the second and third thresholds; and, adjusting the first and second thresholds until the first number equals the second number.

Abstract: A system and method have been provided for determining a frequency tolerance between a generated clock and an input data rate. The invention analyzes beatnotes, externally generated through a comparison of clock and input data rates, and an overflow count of the clock. The occurrence of overflow counts, without intervening beatnotes, indicates that the clock and data rate are close in frequency. The occurrence of beatnotes without intervening overflow counts indicates that the clock and data rates are not close in frequency. Hysteresis is built into the system, preventing the system from indicating an out-of-lock condition when the beatnotes immediate follow the an overflow count, or when the system monitors occasional beatnotes.

Abstract: A system and method are provided for temporally analyzing serial input data. The method comprises: establishing three thresholds; distinguishing present (first) high probability one bit value estimates; distinguishing present high probability zero bit value estimates; and, using a temporal analysis of bit values to distinguish indefinite present bit value estimates. Using a temporal analysis of bit values includes: distinguishing a present bit estimate below first threshold and above the third threshold as a zero if both the past (second) and the future (third) bits are one values and otherwise as a one; and, distinguishing a present bit value estimate above the second threshold and below the third threshold as a one if both the past and future bits are a zero value and otherwise as a zero.