Patents by Inventor Paul Sprague

Paul Sprague has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12335235
    Abstract: Methods, apparatuses, systems, and machine-readable media are disclosed for improving packet filtering efficiency by reducing processing time and/or by reducing memory usage. Any of various types of data structures, such as flat hash maps and/or ruletrees, may be used by a packet filtering appliance to search for cybersecurity policy packet filtering rules that should be applied to in-transit packets. The packet filtering appliance may search the index data structures for matches of search objects, in the form of values that the packet filtering appliance extracts from in-transit packets, to threat indicator matching criteria of the policy rules. Each of the index data structures may map rule identifiers (rule IDs) of policy rules to keys that are based on (or that comprise) the matching criteria of those rules.
    Type: Grant
    Filed: November 11, 2024
    Date of Patent: June 17, 2025
    Assignee: Centripetal Networks, LLC
    Inventors: Sean Moore, Vincent Mutolo, Alexander Chinchilli, Paul Sprague, Christopher T. Rodney, Justin Makoto Leach
  • Publication number: 20250133055
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Application
    Filed: May 21, 2024
    Publication date: April 24, 2025
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Publication number: 20250071092
    Abstract: Methods, apparatuses, systems, and machine-readable media are disclosed for improving packet filtering efficiency by reducing processing time and/or by reducing memory usage. Any of various types of data structures, such as flat hash maps and/or ruletrees, may be used by a packet filtering appliance to search for cybersecurity policy packet filtering rules that should be applied to in-transit packets. The packet filtering appliance may search the index data structures for matches of search objects, in the form of values that the packet filtering appliance extracts from in-transit packets, to threat indicator matching criteria of the policy rules. Each of the index data structures may map rule identifiers (rule IDs) of policy rules to keys that are based on (or that comprise) the matching criteria of those rules.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Inventors: Sean Moore, Vincent Mutolo, Alexander Chinchilli, Paul Sprague, Christopher T. Rodney, Justin Makoto Leach
  • Patent number: 12177180
    Abstract: Methods, apparatuses, systems, and machine-readable media are disclosed for improving packet filtering efficiency by reducing processing time and/or by reducing memory usage. Any of various types of data structures, such as flat hash maps and/or ruletrees, may be used by a packet filtering appliance to search for cybersecurity policy packet filtering rules that should be applied to in-transit packets. The packet filtering appliance may search the index data structures for matches of search objects, in the form of values that the packet filtering appliance extracts from in-transit packets, to threat indicator matching criteria of the policy rules. Each of the index data structures may map rule identifiers (rule IDs) of policy rules to keys that are based on (or that comprise) the matching criteria of those rules.
    Type: Grant
    Filed: May 23, 2024
    Date of Patent: December 24, 2024
    Assignee: Centripetal Networks, LLC
    Inventors: Sean Moore, Vincent Mutolo, Alexander Chinchilli, Paul Sprague, Christopher T. Rodney, Justin Makoto Leach
  • Publication number: 20240396871
    Abstract: Methods, apparatuses, systems, and machine-readable media are disclosed for improving packet filtering efficiency by reducing processing time and/or by reducing memory usage. Any of various types of data structures, such as flat hash maps and/or ruletrees, may be used by a packet filtering appliance to search for cybersecurity policy packet filtering rules that should be applied to in-transit packets. The packet filtering appliance may search the index data structures for matches of search objects, in the form of values that the packet filtering appliance extracts from in-transit packets, to threat indicator matching criteria of the policy rules. Each of the index data structures may map rule identifiers (rule IDs) of policy rules to keys that are based on (or that comprise) the matching criteria of those rules.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 28, 2024
    Inventors: Sean Moore, Vincent Mutolo, Alexander Chinchilli, Paul Sprague, Christopher T. Rodney, Justin Makoto Leach
  • Patent number: 12028311
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: July 2, 2024
    Assignee: Centripetal Networks, LLC
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Patent number: 11902240
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 13, 2024
    Assignee: Centripetal Networks, LLC
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Publication number: 20230336522
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Publication number: 20230179563
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Application
    Filed: January 27, 2023
    Publication date: June 8, 2023
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Patent number: 11570138
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 31, 2023
    Assignee: Centripetal Networks, Inc.
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Publication number: 20220210119
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Application
    Filed: March 18, 2022
    Publication date: June 30, 2022
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Patent number: 11316823
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Centripetal Networks, Inc.
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Publication number: 20220070140
    Abstract: Network devices that are inserted inline into network links and process in-transit packets may significantly improve their packet-throughput performance by not assigning L3 IP addresses and L2 MAC addresses to their network interfaces and thereby process packets through a logical fast path that bypasses the slow path through the operating system kernel. When virtualizing such Bump-In-The-Wire (BITW) devices for deployment into clouds, the network interfaces must have L3 IP and L2 MAC addresses assigned to them. Thus, packets are processed through the slow path of a virtual BITW device, significantly reducing the performance. By adding new logic to the virtual BITW device and/or configuring proxies, addresses, subnets, and/or routing tables, a virtual BITW device can process packets through the fast path and potentially improve performance accordingly. For example, the virtual BITW device may be configured to enforce a virtual path (comprising the fast path) through the virtual BITW device.
    Type: Application
    Filed: August 5, 2021
    Publication date: March 3, 2022
    Inventors: Richard Goodwin, Paul Sprague, Peter Geremia, Sean Moore
  • Patent number: 9555853
    Abstract: A propulsion system for human powered vehicles includes an outer lever having an input end and an output end. An orbiting sprocket is coupled to the output end of the outer lever. A fixed sprocket is also provided, with the orbiting sprocket orbiting around the fixed sprocket. A closed tension-bearing member engages an outer circumference of both the orbiting sprocket and the fixed sprocket. A driveshaft is co-axial with the fixed sprocket, the driveshaft being free to rotate with respect to the fixed sprocket and the crank lever being fixedly connected to the driveshaft and rotationally connected to the orbiting sprocket. A chassis is propelled by the driveshaft. Wherein application of a force on the input end of the outer lever causes the orbiting sprocket to orbit around the fixed sprocket and thereby rotate the crank lever to impart rotation to the driveshaft and propel the chassis.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 31, 2017
    Inventor: Paul Sprague
  • Publication number: 20140210179
    Abstract: A propulsion system for human powered vehicles includes an outer lever having an input end and an output end. An orbiting sprocket is coupled to the output end of the outer lever. A fixed sprocket is also provided, with the orbiting sprocket orbiting around the fixed sprocket. A closed tension-bearing member engages an outer circumference of both the orbiting sprocket and the fixed sprocket. A driveshaft is co-axial with the fixed sprocket, the driveshaft being free to rotate with respect to the fixed sprocket and the crank lever being fixedly connected to the driveshaft and rotationally connected to the orbiting sprocket. A chassis is propelled by the driveshaft. Wherein application of a force on the input end of the outer lever causes the orbiting sprocket to orbit around the fixed sprocket and thereby rotate the crank lever to impart rotation to the driveshaft and propel the chassis.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Inventor: Paul Sprague
  • Patent number: 8520520
    Abstract: A software and hardware system that provides for per flow guaranteed throughput and goodput for packet data flows using network transport protocols that have window-based flow control mechanisms or TCP-friendly flow control mechanisms. The system and method for guaranteed throughput of individual flows in turn enables a method for provisioning link bandwidth among multiple flows and provisioning network throughput and goodput at the granularity of individual flows. The invention also eliminates Layer 3 packet drops for a data flow using window-based flow control or TCP-friendly flow control, which in turn obviates congestion collapse and quality collapse scenarios.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: August 27, 2013
    Assignee: Avaya, Inc.
    Inventors: Sean S. B. Moore, Howard C. Reith, Paul Sprague
  • Publication number: 20070116386
    Abstract: A reclosable tamper-evident package is opened and closed repeatedly by opening and closing a first closure of a package, and when it is desired to close the package and provide an indication of further opening, a second closure is closed that cannot readily be opened. The tamper evident package has a closure assembly that includes a zipper closure arrangement with a slider device. In one embodiment, the slider device is movable between a first axial position and a second axial position. When the slider device is in the first axial position, moving the slider device laterally along the zipper closure arrangement in a first direction closes the first closure. When the slider device is in the second axial position, moving the slider device laterally along the zipper closure arrangement in a first direction closes both the first closure and the second closure.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 24, 2007
    Inventors: Paul Sprague, Peter Boulanger
  • Publication number: 20050286812
    Abstract: A reclosable package that seals an enclosed product and allows the product to be subjected to a retort procedure to cook the product while the product is in the package. The reclosable package is formed from a polypropylene film and includes a zipper closure including a pair of mating closure profiles both formed from a polypropylene material. One of the male or female closure profiles includes a sealing flange having a layer of sealant such that the sealing flange provides a seal for the package below the interaction between the closure profiles. This seal prevents the product from migrating through the profile member during the retort procedure and prior to the package being opened for the first time.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 29, 2005
    Inventors: Paul Sprague, Greg Melchoir
  • Publication number: 20050286810
    Abstract: A reclosable package that seals an enclosed product and allows the product to be subjected to a retort procedure to cook the product while the product is in the package. The reclosable package is formed from a polypropylene film and includes a zipper closure including a pair of mating closure profiles both formed from a polypropylene material. One of the male or female closure profiles includes a sealing flange having a layer of sealant such that the sealing flange provides a seal for the package below the interaction between the closure profiles. This seal prevents the product from migrating through the profile member during the retort procedure and prior to the package being opened for the first time.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 29, 2005
    Inventors: Paul Sprague, Greg Melchoir
  • Publication number: 20050286811
    Abstract: A reclosable package that seals an enclosed product and allows the product to be subjected to a retort procedure to cook the product while the product is in the package. The reclosable package is formed from a polypropylene film and includes a zipper closure including a pair of mating closure profiles both formed from a polypropylene material. One of the male or female closure profiles includes a sealing flange having a layer of sealant such that the sealing flange provides a seal for the package below the interaction between the closure profiles. This seal prevents the product from migrating through the profile member during the retort procedure and prior to the package being opened for the first time.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 29, 2005
    Inventors: Paul Sprague, Greg Melchoir