Patents by Inventor Paul Stephen McLaughlin

Paul Stephen McLaughlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287186
    Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
  • Publication number: 20080224135
    Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
    Type: Application
    Filed: May 28, 2008
    Publication date: September 18, 2008
    Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang, Conal Eugene Murray
  • Patent number: 7388224
    Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
  • Patent number: 7098054
    Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
  • Patent number: 6593660
    Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: July 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Leena P. Buchwalter, Barbara Luther, Paul D. Agnello, John P. Hummel, Terence Lawrence Kane, Dirk Karl Manger, Paul Stephen McLaughlin, Anthony Kendall Stamper, Yun Yu Wang
  • Publication number: 20010053591
    Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 20, 2001
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leena P. Buchwalter, Barbara Luther, Paul D. Agnello, John P. Hummel, Terence Lawrence Kane, Dirk Karl Manger, Paul Stephen Mclaughlin, Anthony Kendall Stamper, Yun Yu Wang
  • Patent number: 6261951
    Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: July 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Leena P. Buchwalter, Barbara Luther, Paul D. Agnello, John P. Hummel, Terence Lawrence Kane, Dirk Karl Manger, Paul Stephen McLaughlin, Anthony Kendall Stamper, Yun Yu Wang