Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Abstract: Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.

Abstract: Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.

Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently restored to an operational state by re-executing or “replaying” a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.