Abstract: A system and method for managing a single premium whole life insurance policy with a rider for providing an accelerated benefit for covered long term care expenses. The system and method provides for accelerated benefits to be tracked and maintained as a lien against the death benefit of the single premium whole life insurance policy. The lien does not directly affect the face value of the single premium whole life insurance policy and permits dividends to continue to be earned from the whole life insurance policy. The lien is applied against the death benefit and serves to reduce the cash value provided should the policy be surrendered.

Abstract: A system and method for managing a whole life insurance policy with a rider for providing an accelerated benefit for covered long term care expenses. The system and method provides for accelerated benefits to be tracked and maintained as a lien against the death benefit of the whole life insurance policy. The lien does not directly affect the face value of the whole life insurance policy and permits dividends to continue to be earned from the whole life insurance policy. The lien is applied against the death benefit and serves to reduce the cash value provided should the policy be surrendered.

Abstract: A method and apparatus for enhancing the performance of a multi-stage pipeline in a digital processor. In one aspect, the stalling of multi-word (e.g. long immediate data) instructions on the word boundary is prevented by defining oversized or “atomic” instructions within the instruction set, thereby also preventing incomplete data fetch operations. In another aspect, the invention comprises delayed decode of breakpoint instructions within the core so as to remove critical path restrictions in the pipeline. In yet another aspect, the invention comprises a multi-function register disposed in the pipeline logic, the register including a bypass mode adapted to selectively bypass or “shortcut” subsequent logic, and return the result of a multi-cycle operation directly to a subsequent instruction requiring the result. Improved data cache integration and operation techniques, and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.