Patents by Inventor Paul Sullivan

Paul Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250037830
    Abstract: An apparatus (800), including: an energy harvesting device (102, 804) configured to harvest energy and to convey the harvested energy; a communication device (102, 806); circuitry (104) configured to be powered by the harvested energy and to be in data communication with the communication device; an unpowered indicator (110) configured to exhibit an excursion indicator only when a temperature excursion of a substance (808) has occurred; and a registration sensor (112) configured to be powered by the harvested energy and when so powered and when the excursion indicator is present, to generate a registration of the excursion indicator. When powered by the harvested energy the circuitry is configured to transmit data comprising the registration of the excursion indicator via the communication device.
    Type: Application
    Filed: December 1, 2022
    Publication date: January 30, 2025
    Inventors: Jeffery A. LETTMAN, Paul SULLIVAN, Randy CARDOZA, Chris EVANS
  • Patent number: 10290399
    Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 14, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Publication number: 20190035518
    Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 31, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Patent number: 10158061
    Abstract: In one embodiment, a method to form a superconductor device includes depositing a crystalline layer having a preferred crystallographic orientation on a substrate and forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer. A metallic layer is formed on the superconductor layer and a mask is provided proximate the substrate to define a protected portion of the oriented superconductor layer and an exposed portion of the oriented superconductor layer. The exposed portion of the oriented superconductor layer is removed without etching the protected portion of the oriented superconductor layer.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 18, 2018
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Publication number: 20180105928
    Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.
    Type: Application
    Filed: December 22, 2017
    Publication date: April 19, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
  • Patent number: 9947441
    Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 17, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Patent number: 9911910
    Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 6, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
  • Patent number: 9887342
    Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 6, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
  • Patent number: 9850569
    Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: December 26, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
  • Patent number: 9768370
    Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: September 19, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
  • Publication number: 20170133575
    Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
  • Patent number: 9590161
    Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 7, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
  • Patent number: 9437392
    Abstract: One embodiment of this ion implanter includes an ion source and a process chamber. This process chamber is connected to the ion source and separated from the ion source by a plurality of extraction electrodes. A carrier holds multiple workpieces. A mask loader in the process chamber connects a mask to the carrier. A transfer chamber and load lock may be connected to the process chamber. The ion implanter is configured to perform either blanket or selective implantation of the workpieces.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: September 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: William T. Weaver, Charles T. Carlson, Joseph C. Olson, James Buonodono, Paul Sullivan
  • Publication number: 20160160344
    Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 9, 2016
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
  • Publication number: 20160163424
    Abstract: In one embodiment, a method to form a superconductor device includes depositing a crystalline layer having a preferred crystallographic orientation on a substrate and forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer. A metallic layer is formed on the superconductor layer and a mask is provided proximate the substrate to define a protected portion of the oriented superconductor layer and an exposed portion of the oriented superconductor layer. The exposed portion of the oriented superconductor layer is removed without etching the protected portion of the oriented superconductor layer.
    Type: Application
    Filed: January 24, 2014
    Publication date: June 9, 2016
    Applicant: Varian Semiconductor Equipment Associated, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Publication number: 20150348680
    Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.
    Type: Application
    Filed: September 17, 2013
    Publication date: December 3, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
  • Publication number: 20150348682
    Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.
    Type: Application
    Filed: November 12, 2013
    Publication date: December 3, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Patent number: 9064760
    Abstract: The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: June 23, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Paul Sullivan
  • Publication number: 20150148236
    Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
  • Publication number: 20150065351
    Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan