Patents by Inventor Paul Sullivan
Paul Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250037830Abstract: An apparatus (800), including: an energy harvesting device (102, 804) configured to harvest energy and to convey the harvested energy; a communication device (102, 806); circuitry (104) configured to be powered by the harvested energy and to be in data communication with the communication device; an unpowered indicator (110) configured to exhibit an excursion indicator only when a temperature excursion of a substance (808) has occurred; and a registration sensor (112) configured to be powered by the harvested energy and when so powered and when the excursion indicator is present, to generate a registration of the excursion indicator. When powered by the harvested energy the circuitry is configured to transmit data comprising the registration of the excursion indicator via the communication device.Type: ApplicationFiled: December 1, 2022Publication date: January 30, 2025Inventors: Jeffery A. LETTMAN, Paul SULLIVAN, Randy CARDOZA, Chris EVANS
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Patent number: 10290399Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.Type: GrantFiled: February 27, 2018Date of Patent: May 14, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Publication number: 20190035518Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.Type: ApplicationFiled: February 27, 2018Publication date: January 31, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Patent number: 10158061Abstract: In one embodiment, a method to form a superconductor device includes depositing a crystalline layer having a preferred crystallographic orientation on a substrate and forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer. A metallic layer is formed on the superconductor layer and a mask is provided proximate the substrate to define a protected portion of the oriented superconductor layer and an exposed portion of the oriented superconductor layer. The exposed portion of the oriented superconductor layer is removed without etching the protected portion of the oriented superconductor layer.Type: GrantFiled: January 24, 2014Date of Patent: December 18, 2018Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INCInventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Publication number: 20180105928Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.Type: ApplicationFiled: December 22, 2017Publication date: April 19, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
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Patent number: 9947441Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.Type: GrantFiled: November 12, 2013Date of Patent: April 17, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Patent number: 9911910Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.Type: GrantFiled: August 29, 2013Date of Patent: March 6, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
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Patent number: 9887342Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.Type: GrantFiled: January 25, 2017Date of Patent: February 6, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
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Patent number: 9850569Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.Type: GrantFiled: November 27, 2013Date of Patent: December 26, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
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Patent number: 9768370Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.Type: GrantFiled: September 17, 2013Date of Patent: September 19, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
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Publication number: 20170133575Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
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Patent number: 9590161Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.Type: GrantFiled: November 27, 2013Date of Patent: March 7, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
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Patent number: 9437392Abstract: One embodiment of this ion implanter includes an ion source and a process chamber. This process chamber is connected to the ion source and separated from the ion source by a plurality of extraction electrodes. A carrier holds multiple workpieces. A mask loader in the process chamber connects a mask to the carrier. A transfer chamber and load lock may be connected to the process chamber. The ion implanter is configured to perform either blanket or selective implantation of the workpieces.Type: GrantFiled: October 26, 2012Date of Patent: September 6, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: William T. Weaver, Charles T. Carlson, Joseph C. Olson, James Buonodono, Paul Sullivan
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Publication number: 20160160344Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.Type: ApplicationFiled: November 27, 2013Publication date: June 9, 2016Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
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Publication number: 20160163424Abstract: In one embodiment, a method to form a superconductor device includes depositing a crystalline layer having a preferred crystallographic orientation on a substrate and forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer. A metallic layer is formed on the superconductor layer and a mask is provided proximate the substrate to define a protected portion of the oriented superconductor layer and an exposed portion of the oriented superconductor layer. The exposed portion of the oriented superconductor layer is removed without etching the protected portion of the oriented superconductor layer.Type: ApplicationFiled: January 24, 2014Publication date: June 9, 2016Applicant: Varian Semiconductor Equipment Associated, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Publication number: 20150348680Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.Type: ApplicationFiled: September 17, 2013Publication date: December 3, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan
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Publication number: 20150348682Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.Type: ApplicationFiled: November 12, 2013Publication date: December 3, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
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Patent number: 9064760Abstract: The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate.Type: GrantFiled: May 20, 2013Date of Patent: June 23, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, Paul Sullivan
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Publication number: 20150148236Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
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Publication number: 20150065351Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Sullivan, Paul Murphy, Kasegn D. Tekletsadik, Bharatwaj Ramakrishnan