Patents by Inventor Paul T. Bennett
Paul T. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8875928Abstract: A soda carbonation retaining apparatus includes a container has a bottom wall, a top wall and a perimeter wall. The bottom wall has an access aperture extending therethrough. The top wall has a nozzle fluidly coupled thereto. A plurality of tracks is mounted to an inner surface of the perimeter wall. A panel is mounted within the housing and is mounted on the tracks. A cover is positionable in a closed position closing the nozzle or in an open position exposing the nozzle. A flexible bag is mounted within the housing and has an upper edge attached to the perimeter wall adjacent to the top wall. The flexible bag is fillable with a carbonated fluid and a volume of the flexible bag is reduced as the panel is moved upwardly toward the nozzle to reduce an amount of free space in the flexible bag.Type: GrantFiled: April 17, 2013Date of Patent: November 4, 2014Inventor: Paul T. Bennett
-
Patent number: 7969196Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.Type: GrantFiled: January 5, 2010Date of Patent: June 28, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Paul T. Bennett, John M. Pigott
-
Publication number: 20100102852Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.Type: ApplicationFiled: January 5, 2010Publication date: April 29, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul T. Bennett, John M. Pigott
-
Patent number: 7667491Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer (12) having first and second inputs and an output and at least one N-type isolation transistor (13, 19) having a source coupled to one or both of the second input and the output. The first input receives the data signal, the second input receives a supply potential, and the output couples to the low voltage logic device. The isolation transistor has a drain for receiving a first potential and is configured to supply a second potential to the output buffer when the gate receives a bias potential. The second potential based on the first potential. The bias potential is greater than the supply potential.Type: GrantFiled: February 24, 2006Date of Patent: February 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Paul T. Bennett, John M. Pigott
-
Patent number: 7595623Abstract: A spread spectrum switching regulator generally includes an reactive circuit portion coupled to the input terminal, a switching element coupled to the reactive circuit portion, and a control circuit portion coupled between the switching element and the output terminal. The switching element has a drive signal characterized by a duty cycle, and the reactive circuitry portion is configured to produce an output voltage at the output terminal responsive to the duty cycle of the drive signal. The control circuit portion is configured to spread the input power across multiple frequencies by adjusting the drive signal of the switching element, thereby reducing input current noise through spread spectrum techniques. The drive signal is responsive to a pseudo-randomly generated ramp signal.Type: GrantFiled: November 20, 2006Date of Patent: September 29, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Paul T. Bennett
-
Patent number: 7538559Abstract: A system (28) includes a microelectronic device (10) including first transistors (22) and second transistors (24), a power supply (40) electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors, a switch (32) in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation, control circuitry in operable communication with the switch, and current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation.Type: GrantFiled: April 9, 2007Date of Patent: May 26, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Paul T. Bennett, Randall C. Gray
-
Publication number: 20080136395Abstract: A spread spectrum switching regulator generally includes an reactive circuit portion coupled to the input terminal, a switching element coupled to the reactive circuit portion, and a control circuit portion coupled between the switching element and the output terminal. The switching element has a drive signal characterized by a duty cycle, and thereactive circuitry portion is configured to produce an output voltage at the output terminal responsive to the duty cycle of the drive signal. The control circuit portion is configured to spread the input power across multiple frequencies by adjusting the drive signal of the switching element, thereby reducing input current noise through spread spectrum techniques. The drive signal is responsive to a pseudo-randomly generated ramp signal.Type: ApplicationFiled: November 20, 2006Publication date: June 12, 2008Inventor: Paul T. Bennett
-
Patent number: 7365584Abstract: Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch (200) when a transistor (210) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor (210) including an inductive load (230) coupled to the transistor, a plurality of current sources (222, 224) coupled to the gate of the transistor, and a clamp (250) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element (260) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.Type: GrantFiled: June 2, 2006Date of Patent: April 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Paul T. Bennett, Randall C. Gray, Matthew D. Thompson
-
Publication number: 20070279069Abstract: A method for testing an electronic assembly (10) is provided. A portion (22) of the electronic assembly is electrically isolated from a remainder (24) of the electronic assembly. Power is provided to the electronic assembly such that a reduced amount of current flows only through the portion of the electronic assembly. The reduced amount of current is determined. A combined amount of current flowing through both the portion and the remainder of the electronic assembly when power is provided to both the portion and the remainder of the electronic assembly is calculated based on the reduced amount of current.Type: ApplicationFiled: April 9, 2007Publication date: December 6, 2007Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul T. Bennett, Randall C. Gray
-
Publication number: 20070279106Abstract: Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch (200) when a transistor (210) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor (210) including an inductive load (230) coupled to the transistor, a plurality of current sources (222, 224) coupled to the gate of the transistor, and a clamp (250) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element (260) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.Type: ApplicationFiled: June 2, 2006Publication date: December 6, 2007Inventors: Paul T. Bennett, Randall C. Gray, Matthew D. Thompson
-
Patent number: 7218119Abstract: A method for testing an electronic assembly (10) is provided. A portion (22) of the electronic assembly is electrically isolated from a remainder (24) of the electronic assembly. Power is provided to the electronic assembly such that a reduced amount of current flows only through the portion of the electronic assembly. The reduced amount of current is determined. A combined amount of current flowing through both the portion and the remainder of the electronic assembly when power is provided to both the portion and the remainder of the electronic assembly is calculated based on the reduced amount of current.Type: GrantFiled: May 31, 2006Date of Patent: May 15, 2007Assignee: Freescale Semiconductors, Inc.Inventors: Paul T. Bennett, Randall C. Gray
-
Patent number: 6906900Abstract: System and method protects power drivers (10) and (12) that are used for airbag deployment. Temperature sensors (38) are strategically located on the integrated circuit (36) to detect temperature levels in power drivers (10) and (12). When the temperature in the power drivers (10) and (12) reaches a maximum level, an output is provided to logic block (26). Current detecting circuit (24) provides an output when the current flowing in power driver (10) reaches a desired level. Timing circuit (28) is activated when it receives the output from current detecting circuit (24). At the expiration of the time, timing circuit (28) provides an output to logic block (26). When logic block (26) receives both outputs, logic block (26) shuts drivers (10) and (12) down. When temperature sensors (38) detects that the temperature in integrated circuit (36) has reached a minimum level, logic block (26) reactivates drivers (10) and (12).Type: GrantFiled: December 19, 2002Date of Patent: June 14, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Paul T. Bennett, Victor A. Chiriac, Tien-Yu Tom Lee, David D. Putti, William E. Edwards
-
Publication number: 20040120382Abstract: System and method protects power drivers (10) and (12) that are used for airbag deployment. Temperature sensors (38) are strategically located on the integrated circuit (36) to detect temperature levels in power drivers (10) and (12). When the temperature in the power drivers (10) and (12) reaches a maximum level, an output is provided to logic block (26). Current detecting circuit (24) provides an output when the current flowing in power driver (10) reaches a desired level. Timing circuit (28) is activated when it receives the output from current detecting circuit (24). At the expiration of the time, timing circuit (28) provides an output to logic block (26). When logic block (26) receives both outputs, logic block (26) shuts drivers (10) and (12) down. When temperature sensors (38) detects that the temperature in integrated circuit (36) has reached a minimum level, logic block (26) reactivates drivers (10) and (12).Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Paul T. Bennett, Victor A. Chiriac, Tien-Yu Tom Lee, David D. Putti, William E. Edwards
-
Patent number: 6348820Abstract: A high-side, low-side driver that controls voltage from a voltage source to an inductive or resistive load includes a power transistor with a gate, a source and a drain. The driver is configured in a high-side configuration when the load is connected between the source and ground and the drain is connected to the voltage source and in a low-side configuration when the load is connected between the drain and the voltage source and the source is connected to ground. A gate drive circuit turns the power transistor on and off. The positive clamp circuit is connected to the drain and the voltage source. The positive clamp circuit provides a recirculation path for inductive energy that is stored in the inductive load when a loss of reverse battery condition occurs or when ground is lost.Type: GrantFiled: July 17, 2000Date of Patent: February 19, 2002Assignee: Motorola, Inc.Inventors: Paul T. Bennett, Randall C. Gray, Michael Garrett Neaves, Joseph V. DeNicholas
-
Patent number: 5872460Abstract: The firing circuit of an inflatable restraint system is tested to verify operation of two FETs in series with a squib which are used to apply current to the squib. For the test the squib is biased to an intermediate voltage and each FET is turned on alone to apply battery or ground voltage to the squib. High and low voltage detectors sense the voltage excursion past respective thresholds to verify FET operation. A current detector for each FET senses a short when its FET is conducting, and a logic circuit immediately turns off the FET to result in a very brief FET on time. In addition, the voltage detectors may be used to detect shorts prior to FET testing and also to turn off or hold off the FETs when a high or low voltage is detected upon FET testing.Type: GrantFiled: October 4, 1996Date of Patent: February 16, 1999Assignee: Delco Electronics Corp.Inventors: Paul T. Bennett, Richard Joseph Ravas, Robert Keith Constable, Randall C. Gray, Terrell Anderson
-
Patent number: 5734317Abstract: An air bag deployment system (10) generates the proper current to activate a squib (74) and deploy an air bag. A separate capacitor (48) powers circuitry in a drive limit controller (54) for providing a variable voltage drive to a MOS device (68) to regulate squib (74) firing current. A switch circuit (38) supplies gate current to a transistor (46) such that an electrical connecting path allows a capacitor (22) to charge a capacitor (48). During squib (74) firing and air bag deployment, the switch circuit (38) provides electrical isolation between the decaying voltage stored on the capacitor (22) that powers the squib (74) current and the capacitor (48) that provides current regulation to the squib (74) from the drive limit controller (54).Type: GrantFiled: July 1, 1996Date of Patent: March 31, 1998Assignee: Motorola, Inc.Inventors: Paul T. Bennett, Randall C. Gray
-
Patent number: 5504448Abstract: A current limit circuit (10/40) for controlling a power transistor (12) has been provided. The current limit circuit includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor for providing an appropriate voltage at the gate electrode of the power transistor when a load is de-coupled from the power transistor. This has the effect of preventing excessive transient current when the load is subsequently coupled to the power transistor. Additionally, the current limit circuit includes circuitry for limiting the current flowing through the power transistor via a sense circuit when the load is coupled to the power transistor.Type: GrantFiled: August 1, 1994Date of Patent: April 2, 1996Assignee: Motorola, Inc.Inventors: Paul T. Bennett, Robert P. Dixon
-
Patent number: 5483406Abstract: An overvoltage protection circuit (11) for decoupling circuitry (12) from a voltage applied to an input (38). The overvoltage protection circuit (11) is integrated on an integrated circuit along with the circuitry (12). The overvoltage protection circuit (11) comprises a sense circuit (13), a timing circuit (14), a decoupling circuit (16), and a circuit (17). The sense circuit (13) detects when the voltage applied to the input (38) exceeds a threshold voltage. The timing circuit (14) is responsive to the sense circuit (13) and determines when the voltage exceeds the threshold voltage for a predetermined time. The decoupling circuit (16) is responsive to the timing circuit (14) and decouples the circuitry from the voltage applied to the input (38). The circuit (17) generates a logic signal indicating the circuitry has been decoupled.Type: GrantFiled: September 30, 1993Date of Patent: January 9, 1996Assignee: Motorola, Inc.Inventors: Paul T. Bennett, Randall C. Gray, John M. Pigott
-
Patent number: 5455579Abstract: A paging receiver device and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory of the paging receiver. In response to a paging user's request, the digitized stored message is recalled from memory, reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.Type: GrantFiled: August 7, 1990Date of Patent: October 3, 1995Assignee: Motorola, Inc.Inventors: Paul T. Bennett, David F. Willard, Omid Tahernia, James C. Page, Allan I. Spiro, Frank E. Lambrecht
-
Patent number: 5428352Abstract: A closed loop circuit for controlling a differential capacitive sensor has been provided wherein the differential capacitive sensor includes a rigid top and bottom plate, and a movable middle plate. The closed loop circuit has a clock period which is divided into three separate sub-periods: the force period, the reset period and the sense period. During the force period, a top or a bottom electrostatic force is applied such that the middle plate is attracted towards the top plate or the bottom plate, respectively. During the reset period, substantially equal voltages are applied to all three plates. Finally, during the sense period, the voltage on the middle plate is sensed to determine whether the middle plate is closer to the top plate or to the bottom plate. Further, the result during the sense period will be utilized to determine whether to apply a top force or a bottom force during the next subsequent force period.Type: GrantFiled: January 31, 1992Date of Patent: June 27, 1995Assignee: Motorola, Inc.Inventor: Paul T. Bennett