Abstract: Briefly, in accordance with one embodiment of the invention, a method of reducing the power consumption of a pipelined signal processor embedded in an integrated circuit (IC), after applying power to the IC, comprises the step of: applying a sufficient number of internally generated clock pulses to the pipelined signal processor so as to place at least one bus in the signal processor pipeline in a predetermined state. Briefly, in accordance with another embodiment of the invention, an integrated circuit comprises: a power-up reset circuit for a pipelined signal processor. The power-up reset circuit includes a counter and a digital signal oscillator. The digital signal oscillator and counter are coupled in a configuration so as to provide a predetermined number of clock pulses substantially in response to a power-up signal. The configuration is adapted to be coupled to the pipelined signal processor.

Abstract: Frequency generators that may be programmed are utilized in a wide variety of applications. Typical applications include radio and television receivers and transmitters, and computer devices that must operate at different clock rates, or be compatible with systems that operate at different clock rates. The present technique provides for programmably generating a frequency. A ring oscillator receives at least one operating voltage through a programmable array of field effect transistors. Digitally selecting a given set of the transistors provides a given operating current for the ring, which establishes the frequency of operation. In one embodiment, the technique is implemented in a CMOS integrated circuit. This technique provides for more rapid frequency changes in a low-power circuit than can be obtained with typical prior-art techniques (e.g., a phase-locked loop).