Patents by Inventor Paul T. Hui

Paul T. Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100015793
    Abstract: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned to form a first opening to contact the last interconnect layer. The polyimide layer is also patterned to leave a second opening that is inside and thus smaller than the first opening through the passivation. The barrier layer is then deposited in contact with the last interconnect layer and bounded by the polyimide layer. The bond pad is then formed in contact with the barrier, and a wire bond is then made to the bond pad.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 21, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James Jen-Ho Wang, Paul T. Hui
  • Patent number: 7615866
    Abstract: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned to form a first opening to contact the last interconnect layer. The polyimide layer is also patterned to leave a second opening that is inside and thus smaller than the first opening through the passivation. The barrier layer is then deposited in contact with the last interconnect layer and bounded by the polyimide layer. The bond pad is then formed in contact with the barrier, and a wire bond is then made to the bond pad.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: November 10, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James Jen-Ho Wang, Paul T. Hui
  • Publication number: 20070275549
    Abstract: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned to form a first opening to contact the last interconnect layer. The polyimide layer is also patterned to leave a second opening that is inside and thus smaller than the first opening through the passivation. The barrier layer is then deposited in contact with the last interconnect layer and bounded by the polyimide layer. The bond pad is then formed in contact with the barrier, and a wire bond is then made to the bond pad.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 29, 2007
    Inventors: James Jen-Ho Wang, Paul T. Hui