Abstract: A system and methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. The system is configured with an upper bank of heat elements perpendicular to the gas flow path, such that when the substrate is heated, the temperature across the substrate can be maintained relatively uniform via zoned heating. Advantageously, a short, low temperature process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake.

Abstract: A system and methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. The system is configured with an upper bank of heat elements perpendicular to the gas flow path, such that when the substrate is heated, the temperature across the substrate can be maintained relatively uniform via zoned heating. Advantageously, a short, low temperature process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake.

Abstract: A system and methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. The system is configured with an upper bank of heat elements perpendicular to the gas flow path, such that when the substrate is heated, the temperature across the substrate can be maintained relatively uniform via zoned heating. Advantageously, a short, low temperature process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake.

Abstract: A substrate processing system has computer controlled injectors. The computer is configured to adjust a plurality of injectors, such as during deposition of a graded layer, between depositions of two different layers, or between deposition and chamber clean steps.

Abstract: A semiconductor processing apparatus having a processing chamber defined by a plurality of walls and a substrate support to support a substrate within the processing chamber.

Abstract: The invention is a carrier comprising three support elements connected by an underlying frame. The periphery of a wafer rests upon the support elements. The invention also comprises a wafer handler with a plurality of arms. Spacers space the carrier above a base plate associated with a station in a wafer handling area. An arm slides beneath the frame and between the spacers, but the handler does not contact the wafer. A method of using the handler and carrier is provided where the handler lifts and rotates the carrier with the wafer through various stations in a wafer handling area. A control device reduces the handler speed only at critical points of the processing cycle. The handler is capable of moving a plurality of carriers and wafers simultaneously.

Abstract: The invention is a carrier comprising three support elements connected by an underlying frame. The periphery of a wafer rests upon the support elements. The invention also comprises a wafer handler with a plurality of arms. Spacers space the carrier above a base plate associated with a station in a wafer handling area. An arm slides beneath the frame and between the spacers, but the handler does not contact the wafer. A method of using the handler and carrier is provided where the handler lifts and rotates the carrier with the wafer through various stations in a wafer handling area. The handler is capable of moving a plurality of carriers and wafers simultaneously.