Patents by Inventor Paul T. Nguyen

Paul T. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067926
    Abstract: Methods are provided for the cell-based delivery of collagen VII for the treatment of Epidermolysis Bullosa and corneal erosion. The disclosure also provides a composition and a pharmaceutical composition comprises, comprise, or alternatively consist essentially of, or yet further consist of a keratinocyte sheet or a corneal cell sheet.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Inventors: Zurab Siprashvili, Ngon T. Nguyen, M. Peter Marinkovich, Jean Tang, Alfred T. Lane, Paul A. Khavari
  • Patent number: 7555690
    Abstract: Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device under test and a second connector coupled to receive compressed test data by way of test equipment. The device also comprises a decompressor coupled to receive compressed test data, and provided decompressed test data to the device under test. Embodiments implementing two different clocks to improve the speed of testing integrated circuits are also disclosed. Various methods for coupling test signals to a device under test are also disclosed.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: June 30, 2009
    Assignee: XILINX, Inc.
    Inventors: Yi-Ning Yang, Arthur H. Khu, Jin-Feng Chou, Paul T. Nguyen
  • Patent number: 7308632
    Abstract: A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: December 11, 2007
    Assignee: Xilinx, Inc.
    Inventors: Himanshu J. Verma, Paul T. Nguyen, Paul A. Swartz