Abstract: Based on measurement reports reported to a base station by a plurality of UEs, the base station or a data system may dynamically configure a location of a physical random access control channel (PRACH) defined by the base station such that the PRACH is located in an optimal location. In one example, a data system may receive a plurality of subband CQI reports that includes one or more subband CQI values reported to the base station by each of a plurality of UEs served by the base station. The data system may determine, based on the plurality of subband CQI reports, that a particular range of resource blocks has a highest reported downlink air interface quality. And the data system may cause the base station define a PRACH instance in the particular range of resource blocks for carrying random access requests from the plurality of UEs to the base station.

Abstract: A method for dynamically selecting one of a plurality of base stations for provision of timing information. A base station compares satellite signal strengths measured at satellite-positioning-system receivers of a plurality of base stations, such as the plurality of base stations in a local area network (LAN) for instance. The base station then selects one of the plurality of base stations to provide timing information based at least in part on the comparison, such as the one base station having the greatest satellite signal strength for instance. The base station then operates according to timing information indicated by satellite data from the selected base station. Advantageously, this method can help to increase the accuracy and reliability of the timing information.

Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.

Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i.e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.

Abstract: A programmable device with an improved system for loading configuration data compresses configuration data by composing configuration data out of pairs of control words and data words. The configuration data is divided into configuration words. Each configuration word is further divided into a number of configuration blocks. In a control word/data word pair, the control word determines which configuration blocks in the configuration word will be loaded with the data word. Each configuration block designated by the control word will be simultaneously loaded with the data word. By taking advantage of the symmetry within the control word, typically only a small number of control word/data word pairs will be required to load a complete control word. If a given control word does not have sufficient symmetry, the programmable device can instead use an alternate system for loading the configuration word.

Abstract: A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.

Abstract: Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application is identified. A test is then performed only on the set and a test result is generated. Defective resources may be replaced. The PLD is identified as defective only if one of the resources associated with the customer application is defective. Such application specific testing allows the ability of the customer to perform in-system testing, the reduction of the time required for testing the PLD, and the testing of PLDs based on knowledge of the customer's application, among other advantages.

Abstract: Circuits, methods, and apparatus for output response analyzers that may be used during integrated circuit testing. Current output test data is compared with previous output test data. In this way, repetitive test patterns such as checkerboards may be employed while limiting circuit complexity. The outputs of several built-in self-test circuits may be combined into as few as one signal that may be provided as a test output.