Abstract: A method having a negative output voltage at a negative output terminal of a charge pump tracking a positive output voltage at a positive output terminal of the charge pump. The charge pump comprises a plurality of switches and each of the plurality of switches has a serially coupled resistance. The method comprises selecting the serially coupled resistance for at least one of the plurality of switches to be different to each of the other respective serially coupled resistances associated to the other switches.

Abstract: A switching power converter with an input terminal configured to receive a first input voltage; an output terminal configured to provide an output current to a load, wherein the output current has a peak value and an average value; a power switch; a first loop coupled to the input terminal, wherein the first loop configured to generate a first output signal based on the first input voltage; a second loop configured to generate a second output signal based on the output current; a multiplier configured to generate a multiplying signal based on multiplying the first output signal with the second output signal; and a driving circuit configured to generate a driving signal based on the multiplying signal to control the power switch, so as to reduce the ratio between the peak value and the average value of the output current.

Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: The present application discloses a control circuit of a switching power converter, wherein the switching power converter comprises a power switch, and is configured to convert an input voltage into an output voltage, the control circuit comprises: a first time generating circuit configured to generate a first time signal; a phase lock circuit configured to generate a second time signal; and a switching signal generating circuit configured to generate a switching signal to control the ON and OFF switching of the power switch. The phase lock circuit generates the second time signal in accordance with the frequency difference between the switching signal and a reference clock signal, so as to get the frequency of the switching signal to be substantially equal to the frequency of the reference clock signal.

Abstract: A method having a negative output voltage at a negative output terminal of a charge pump tracking a positive output voltage at a positive output terminal of the charge pump. The charge pump comprises a plurality of switches and each of the plurality of switches has a serially coupled resistance. The method comprises selecting the serially coupled resistance for at least one of the plurality of switches to be different to each of the other respective serially coupled resistances associated to the other switches.

Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: A switching power converter with an input terminal configured to receive a first input voltage; an output terminal configured to provide an output current to a load, wherein the output current has a peak value and an average value; a power switch; a first loop coupled to the input terminal, wherein the first loop configured to generate a first output signal based on the first input voltage; a second loop configured to generate a second output signal based on the output current; a multiplier configured to generate a multiplying signal based on multiplying the first output signal with the second output signal; and a driving circuit configured to generate a driving signal based on the multiplying signal to control the power switch, so as to reduce the ratio between the peak value and the average value of the output current.

Abstract: The present application discloses a control circuit of a switching power converter, wherein the switching power converter comprises a power switch, and is configured to convert an input voltage into an output voltage, the control circuit comprises: a first time generating circuit configured to generate a first time signal; a phase lock circuit configured to generate a second time signal; and a switching signal generating circuit configured to generate a switching signal to control the ON and OFF switching of the power switch. The phase lock circuit generates the second time signal in accordance with the frequency difference between the switching signal and a reference clock signal, so as to get the frequency of the switching signal to be substantially equal to the frequency of the reference clock signal.

Abstract: Circuit configurations for a high power switch-mode voltage regulator circuit is disclosed that include an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources and a plurality of gate driver circuits. Each gate driver circuit is coupled to a gate and dedicated to driving only one MOS switching transistor.

Abstract: A fault detection circuit and a short-circuit detection circuit for a Cold Cathode Fluorescent Lamp (CCFL) driver integrated circuit having a power bridge and a CCFL load are disclosed that includes a reference circuit operable to generate a reference current in response to an external component, a replica component having a dimension substantially less than the components of the power bridge, a multiplexer circuit, and a comparator circuit. The replica component and the multiplexer circuit pass the reference current and the replica current to the comparator circuit respectively.

Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.

Abstract: Circuit configurations for a high power switch-mode voltage regulator circuit is disclosed that include an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources and a plurality of gate driver circuits. Each gate driver circuit is coupled to a gate and dedicated to driving only one MOS switching transistor.

Abstract: A circuit configuration for a high power switch-mode voltage regulator circuit is disclosed that includes an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources, and a plurality of gate driver circuits. Each gate driver circuit is coupled substantially close to the gate and dedicated to driving only one MOS switching transistor.

Abstract: The present disclosure introduces a simple method and apparatus for converting DC power to AC power for driving discharge lamps such as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), or a flat fluorescent lamp (FFL). Among other advantages, the invention allows the proper protection under short circuit conditions for applications where the normal lamp current is greater than safe current limit.

Abstract: A circuit configuration for a high power switch-mode voltage regulator circuit is disclosed that includes an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources, and a plurality of gate driver circuits. Each gate driver circuit is coupled substantially close to the gate and dedicated to driving only one MOS switching transistor.

Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.

Abstract: A fault detection circuit and a short-circuit detection circuit for a Cold Cathode Fluorescent Lamp (CCFL) driver integrated circuit having a power bridge and a CCFL load are disclosed that includes a reference circuit operable to generate a reference current in response to an external component, a replica component having a dimension substantially less than the components of the power bridge, a multiplexer circuit, and a comparator circuit. The replica component and the multiplexer circuit pass the reference current and the replica current to the comparator circuit respectively.

Abstract: The present disclosure introduces a simple method and apparatus for converting DC power to AC power for driving discharge lamps such as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), or a flat fluorescent lamp (FFL). Among other advantages, the invention allows the proper protection under short circuit conditions for applications where the normal lamp current is greater than safe current limit.

Abstract: The present disclosure introduces a simple method and apparatus for converting DC power to AC power for driving discharge lamps such as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), or a flat fluorescent lamp (FFL). Among other advantages, the invention allows the proper protection under short circuit conditions for applications where the normal lamp current is greater than safe current limit.

Abstract: The present disclosure introduces a simple method and apparatus for converting DC power to AC power for driving discharge lamps such as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), or a flat fluorescent lamp (FFL). Among other advantages, the invention allows the proper protection under short circuit conditions for applications where the normal lamp current is greater than safe current limit.