Abstract: Packet processing circuitry comprises a look-up engine and a processor. The look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM. The look-up engine retrieves a first context structure based on the first result. The look-up engine builds a summation block using the first context structure and transfers the summation block. The processor receives and processes the summation block to control handling of the communication packet.

Abstract: Packet processing circuitry comprises a processor and a look-up engine. The look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM. The look-up engine generates a second selector based on the first result. The look-up engine transfers the second selector to the CAM and receives a corresponding second result from the CAM. The look-up engine retrieves a first context structure based on the second result. The look-up engine builds a summation block using the first context structure and transfers the summation block to the processor. The processor receives and processes the summation block to control handling of the communication packet.

Abstract: Packet processing circuitry comprises a processor and a look-up engine. For a first communication packet, the look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM, retrieves a first context structure based on the first result and builds a summation block using the first context structure, transfers the summation block to the processor, writes a second selector to the CAM and receives a corresponding second result from the CAM, and writes the summation block to a memory location corresponding to the second result. For a second communication packet, the look-up engine transfers the second selector to the CAM and receives the corresponding second result from the CAM, retrieves the summation block based on the second result and transfers the summation block to the processor The processor receives and processes the summation block to control handling of the first and second communication packets.

Abstract: Packet processing circuitry comprises a look-up engine and a processor. The look-up engine transfers a selector to a CAM and receives a corresponding result from the CAM. The look-up engine retrieves a context structure from a context memory based on the result and transfers the context structure to the processor. The processor receives and processes the context structure to control handling of the communication packet. The processor modifies the context structure and transfers the modified context structure to the look-up engine. The processor generates an update instruction and transfers the update instruction to the look-up engine. The look-up engine receives the update instruction and the modified context structure. The look-up engine automatically writes the modified context structure to the context memory in response to the update instruction.

Abstract: A content-addressable memory is comprised of processing logic and selector logic. The processing logic receives a first selector including packet header information from the packet processing circuitry. The processing logic transfers the first selector to the selector logic. The processing logic generates additional selectors and transfers the additional selectors to the selector logic. The selector logic receives and processes selectors for matches and provides results corresponding to the matches. The processing logic receives the results from the selector logic and transfers at least some of the results that point to packet processing context structures to the packet processing circuitry.

Abstract: Packet processing circuitry comprises a processor and a look-up engine. The look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM. The look-up engine generates a second selector based on the first result. The look-up engine transfers the second selector to the CAM and receives a corresponding second result from the CAM. The look-up engine retrieves a first context structure based on the second result. The look-up engine builds a summation block using the first context structure and transfers the summation block to the processor. The processor receives and processes the summation block to control handling of the communication packet.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. A group of bits comprises a primary scoreboard indicative of the scheduling status for cell time slots in a periodic container of cells, with each bit indicating the availability of a corresponding cell time slot. A connection identifier (ID) table is maintained with each location in the table corresponding to one of the cell time slots and thus a single primary scoreboard bit. A cell scheduling instruction specifies a connection ID for a virtual connection on an ATM transmission link. A processor searches the primary scoreboard until a bit corresponding to an available cell time slot is located, reserves the located cell slot by setting the corresponding bit, and stores the connection ID in the corresponding location in the connection ID table. A cell servicing instruction specifies an address in the connection ID table.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. A group of bits comprises a primary scoreboard indicative of the scheduling status for cell time slots in a periodic container of cells, with each bit indicating the availability of a corresponding cell time slot. A connection identifier (ID) table is maintained with each location in the table corresponding to one of the cell time slots and thus a single primary scoreboard bit. A cell scheduling instruction specifies a connection ID for a virtual connection on an ATM transmission link. A processor searches the primary scoreboard until a bit corresponding to an available cell time slot is located, reserves the located cell slot by setting the corresponding bit, and stores the connection ID in the corresponding location in the connection ID table. A cell servicing instruction specifies an address in the connection ID table.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a cell buffer RAM (CBR) memory space gathering protocol which allows unused portions of a number of cell buffers to be addressed as a contiguous virtual memory space. The space gathering protocol may utilize a CPU or direct memory access (DMA) controller in an ATM cell processor to set a gather bit appended to a virtual CBR address. An address generator in the CBR detects the gather bit and translates those virtual addresses which include a set gather bit to physical addresses into the CBR memory space. The translation is performed by setting certain bits of the physical address to predetermined states to reach the unused 8 bytes at the bottom of any given 64-byte cell buffer, and shifting certain bits of the virtual address to other positions in the physical address to move from cell buffer to cell buffer in the contiguous virtual space.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a modulo arithmetic feature which permits branching on the modulo portion of the result of an arithmetic operation. An arithmetic logic unit (ALU) or other processor instruction is modified to include a modulo field which specifies the number of right to left bits after which the result of the corresponding ALU operation will be truncated. Conditional branch instructions such as branch on zero result, branch on non-zero result, branch on negative result, branch on carry and branch on overflow may be configured to operate only on the modulo portion of the ALU instruction result and/or on a carry out of the most significant bit (MSB) position of the modulo portion.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor implements a "bubble" count technique which efficiently accommodates multiple layers of scheduling requests and/or external cell sources. In the case of multiple layers of scheduling requests, first and second primary scoreboards are provided for scheduling/servicing of, for example, higher and lower priority traffic, higher and lower cell rate traffic, or externally and internally generated traffic, respectively. A bubble count is maintained for the second scoreboard, and the count is incremented each time the first scoreboard is serviced and decremented each time an idle slot is encountered on the second scoreboard but not queued for transmission. Scheduling requests for the second scoreboard are then made at a target time plus the bubble count.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple instruction which provides a burst transfer of a data block from an external control memory, and allows the result of a subsequent operation on a loaded value to be automatically written back to the control memory location from which it was previously read. The instruction may specify the address in the control memory of a data block to be retrieved, a destination register in a CPU register file into which the first retrieved halfword of a data block will be loaded, and a total number of halfwords to be retrieved. The instruction includes a link field option which directs the storage of information linking the processor registers which receive the retrieved halfwords to the control memory locations from which the halfwords were read.