Abstract: Methods and systems support bridging between end devices conforming to a legacy bus specification and a host processor using an updated bus specification, for example the latest PCIe specification or Compute Express Link (CXL). A hardware bridge can serve as an intermediary between the legacy I/O devices and the host processor. The hardware bridge has a hardware infrastructure and performs a hardware virtualization of the legacy I/O devices such that their legacy hardware is emulated by a virtual interface. The hardware bridge can surface the virtual interface to the host processor, enabling these I/O devices to appear to the host processor as an end device communicating in accordance with the updated bus specification. The hardware virtualization can involve emulating the I/O devices using scalable I/O Virtualization (SIOV) queue pairs, providing flexible and efficient translation between the legacy and updated specifications.

Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Abstract: A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: Embodiments include methods, apparatus, and systems for converting resets in a shared I/O system. One embodiment includes a method that propagates a first type of reset from a host computer to a multi-function device that shares I/O operations with other hosts. The first type of reset is converted to a second type of reset to prevent the host from resetting functions bound to the other hosts at the multi-function device.

Abstract: A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.

Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

Abstract: A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.

Abstract: A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.

Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Abstract: Embodiments include methods, apparatus, and systems for converting resets in a shared I/O system. One embodiment includes a method that propagates a first type of reset from a host computer to a multi-function device that shares I/O operations with other hosts. The first type of reset is converted to a second type of reset to prevent the host from resetting functions bound to the other hosts at the multi-function device.

Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.

Abstract: There is provided a system and method of controlling transaction flow in a communications interface. An exemplary system comprises a first buffer configured to hold packets of a first packet type, and a second buffer configured to hold packets of a second packet type. An exemplary system also comprises a counter configured to track a delay-reference of packets held in the second buffer. An exemplary system also comprises a controller configured to receive packets from a host and send packets of the first packet type to the first buffer and to send packets of the second packet type to the second buffer, the controller being further configured to stop receiving packets if the delay-reference meets or exceeds a specified threshold.

Abstract: In a shared I/O environment, a method for dynamic memory bandwidth adjustment adjusts memory bandwidth between a host server and an I/O function by increasing memory bandwidth to higher priority functions while decreasing memory bandwidth to lower priority functions without bringing down the link between the host and I/O devices.

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract: A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.