Abstract: A method, apparatus, and computer program product for cell placement in an integrated circuit design that use the principles of diffusion.

Abstract: A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts within the physical design automation area including global and detailed placement, physical synthesis, and ECO (Engineering Change Order) mode for timing/design closure The method involves capturing a view of a given placement, solving a global two-dimensional area migration model and locally perturbing the cells to resolve the overlaps with minimal changes to the given placement. The method first captures a two-dimensional view of the placement including blockage-space, free-space and the given location of cells by defining physical regions. The desired global area migration across the physical regions of the placement image is determined such that it satisfies area capacity-demand constraints.

Abstract: A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method relies upon a “look ahead” technique, combined with any generic cost function that can be used to set placement directives. These placement directives include net weights and cell spreading. The method of performing the placement involves the iterative reuse of the process of successive partitioning. This iterative reuse establishes the capability of looking ahead to determine what is to happen. Based on the look ahead, it is possible to evaluate the qualities of the placement about to be generated. The method proceeds through the placement from while maintaining the current state of the placement along with the look-ahead state of the placement.

Abstract: A method of designing a layout of an integrated circuit, by grouping a plurality of logic cells in a region of the integrated circuit into at least two separate clusters, placing the clusters in the region of the integrated circuit to optimize total wire length between the clusters (e.g., using quadratic placement), partitioning the region, and recursively repeating the placing and the partitioning to place the logic cells in progressively smaller bins of the region, while ungrouping the clusters. Clustering preferably groups smaller logic cells before grouping larger logic cells, and can be repeated iteratively with further re-grouping of the clusters, prior to the placing and partitioning. The number of iterations can be limited by an operator input parameter. A given cluster is ungrouped when its size is larger than a fraction of total free space available in a corresponding bin. This fraction can also be an operator input parameter.

Abstract: A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout.

Abstract: A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value.

Abstract: A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts within the physical design automation area including global and detailed placement, physical synthesis, and ECO (Engineering Change Order) mode for timing/design closure The method involves capturing a view of a given placement, solving a global two-dimensional area migration model and locally perturbing the cells to resolve the overlaps with minimal changes to the given placement. The method first captures a two-dimensional view of the placement including blockage-space, free-space and the given location of cells by defining physical regions. The desired global area migration across the physical regions of the placement image is determined such that it satisfies area capacity-demand constraints.

Abstract: A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method relies upon a “look ahead” technique, combined with any generic cost function that can be used to set placement directives. These placement directives include net weights and cell spreading. The method of performing the placement involves the iterative reuse of the process of successive partitioning. This iterative reuse establishes the capability of looking ahead to determine what is to happen. Based on the look ahead, it is possible to evaluate the qualities of the placement about to be generated. The method proceeds through the placement from while maintaining the current state of the placement along with the look-ahead state of the placement.

Abstract: A method of designing a layout of an integrated circuit first places logic cells in an initial region of the integrated circuit using a first placement algorithm then, after partitioning the initial region into two or more partitioned regions, uses a second placement algorithm (different from the first placement algorithm) to place a portion of the logic cells in at least one of the partitioned regions. The placement algorithms are preferably quadratic placement algorithms such as the conjugate gradient placement algorithm and the successive over-relaxation placement algorithm. The selection of the particular placement algorithm to be used may be based on, e.g., the cut level or the number moveable objects for the given partition region.

Abstract: A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.