Patents by Inventor Paul W. Brazis

Paul W. Brazis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9869719
    Abstract: A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 16, 2018
    Assignee: UL LLC
    Inventor: Paul W. Brazis, Jr.
  • Publication number: 20170097391
    Abstract: A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventor: Paul W. Brazis, JR.
  • Patent number: 9551751
    Abstract: A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: January 24, 2017
    Assignee: UL LLC
    Inventor: Paul W. Brazis, Jr.
  • Patent number: 9451247
    Abstract: A camera testing apparatus includes a frame assembly, a control unit, and a plurality of first light sources and second light sources coupled to the frame assembly and in communication with the control unit. Each of the first and second light sources is in one of an illuminated first state or a non-illuminated second state, and each of the plurality of first and second light sources is adapted to be within a field of vision of a camera disposed remote from the first and second light sources. The control unit sends a first command to each of the first light sources to change a first operational parameter. The control unit sends a second command to a first one of the second light sources to illuminate at a first brightness and a third command to a second one of the second light sources to illuminate at a second brightness.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: September 20, 2016
    Assignee: UL LLC
    Inventors: Fan He, Paul W. Brazis, Jr.
  • Publication number: 20150146016
    Abstract: A camera testing apparatus includes a frame assembly, a control unit, and a plurality of first light sources and second light sources coupled to the frame assembly and in communication with the control unit. Each of the first and second light sources is in one of an illuminated first state or a non-illuminated second state, and each of the plurality of first and second light sources is adapted to be within a field of vision of a camera disposed remote from the first and second light sources. The control unit sends a first command to each of the first light sources to change a first operational parameter. The control unit sends a second command to a first one of the second light sources to illuminate at a first brightness and a third command to a second one of the second light sources to illuminate at a second brightness.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Fan He, Paul W. Brazis, JR.
  • Publication number: 20120319709
    Abstract: A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: UNDERWRITERS LABORATORIES INC.
    Inventor: Paul W. Brazis, JR.
  • Publication number: 20100163861
    Abstract: A method and apparatus for an optically transparent field effect transistor on a substrate. The gate electrode, the dielectric, the semiconducting layer, the source electrode, and the drain electrode are optically transparent layers of nanoparticles that are formed using one or more graphic arts printing processes. The dielectric layer is in contact with the gate electrode, the semiconducting layer is in contact with the dielectric layer, and the source and drain electrodes are in contact with the semiconducting layer.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: Motorola, Inc.
    Inventor: Paul W. Brazis, JR.
  • Patent number: 7550998
    Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: June 23, 2009
    Assignee: Motorola, Inc.
    Inventors: Paul W. Brazis, Daniel R. Gamota, Kin P. Tsui, John B. Szczech, Jie Zhang
  • Patent number: 7538683
    Abstract: An object (201) (such as a containment mechanism) supports both a functional electrical circuit (203) and an electrical circuit (202) to which the functional electrical circuit is responsive. In a preferred approach the functional electrical circuit has both a low power state of operation and a higher power state of operation. Upon detecting (104) that an area of connectivity of the electrical circuit has been severed (via, for example, corresponding manipulation of the object itself), the functional electrical circuit responsively operates (106) using the higher power state of operation.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: May 26, 2009
    Assignee: Motorola, Inc.
    Inventors: Mansour Toloo, Hakeem B. Adewole, Paul W. Brazis, Daniel R. Gamota, Julius S. Gyorfi, Swee M. Mok, John B. Szczech, Jie Zhang
  • Publication number: 20090098668
    Abstract: A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing (103) of the test structure with respect to at least one static (i.e., relatively unchanging) electrical characteristic metric. The static electrical characteristic metric (or metrics) of choice will likely vary with the application setting but can include, for example, a measure of electrical resistance, a measure of electrical reactance, and/or a measure of electrical continuity. Optionally (though preferably) the semiconductor device printing process itself is then adjusted (105) as a function, at least in part, of this metric.
    Type: Application
    Filed: November 13, 2008
    Publication date: April 16, 2009
    Applicant: Motorola, Inc.
    Inventors: Paul W. Brazis, Daniel R. Gamota, Krishna Kalyanasundaram, Jie Zhang, Krishna D. Jonnalagadda
  • Publication number: 20090057662
    Abstract: A low-temperature process for creating a semiconductive device by printing a liquid composition containing semiconducting nanoparticles. The semiconductive device is formed on a polymeric substrate by printing a composition that contains nanoparticles of inorganic semiconductor suspended in a carrier, using a graphic arts printing method. The printed deposit is then heated to remove substantially all of the carrier from the printed deposit. The low-temperature process does not heat the substrate or the printed deposit above 300° C. The mobility of the resulting semiconductive device is between about 10 cm2/Vs and 200 cm2/Vs.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Applicant: MOTOROLA, INC.
    Inventors: Paul W. Brazis, Daniel R. Gamota, Dale R. McClure, Andrew F. Skipor, Jie Zhang
  • Patent number: 7492604
    Abstract: An electronic apparatus, includes a plurality of electronic modules, each having a maximum thickness of no more than 90 microns, each comprising a substrate having a two sided edge connection pattern. The electronic modules are arranged adjacent to each other. Each pad of a first set of connection pads on a first electronic module is conductively connected to an opposing pad of a second set of connection pads of a second electronic module. The first set of connection pads is separated from the second set of connection pads by electrically conductive material that is less than 15 microns thick.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: February 17, 2009
    Assignee: Motorola, Inc.
    Inventors: Paul W. Brazis, Marc K. Chason, Daniel R. Gamota, Krishna Kalyanasundaram
  • Patent number: 7399656
    Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: July 15, 2008
    Assignee: Motorola, Inc.
    Inventors: Jie Zhang, Paul W. Brazis, Daniel R. Gamota, Krishna Kalyanasundaram, Min-Xian M. Zhang
  • Publication number: 20080111806
    Abstract: A paperstock card (201) is integrally combined (102) with each of a printed dynamic display (203), a printed display control circuit (202), and a printed power source (204). So configured, the paperstock card can offer, in a relatively economical and flexible manner, textual and/or image-based content of choice. In addition, by this approach, some or all of this content can comprise animated content. By one approach, for example, this could even comprise video content depicting the person who presents the paperstock card to a given recipient.
    Type: Application
    Filed: November 10, 2006
    Publication date: May 15, 2008
    Applicant: MOTOROLA, INC.
    Inventors: Gabriela A. Dyrc, Hakeem B. Adewole, Paul W. Brazis, Katherine M. Devanie
  • Patent number: 7355225
    Abstract: An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach the first electrode has a surface area that is reduced notwithstanding the aforementioned established perimeter. This, in turn, aids in reducing any corresponding parasitic capacitance. This reduction in surface area may be accomplished, for example, by providing openings (203) through certain portions of the first electrode.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: April 8, 2008
    Assignee: Motorola, Inc.
    Inventors: Paul W. Brazis, Daniel R. Gamota, Krishna Kalyanasundaram, Jie Zhang
  • Patent number: 7244626
    Abstract: Two or more semiconductor devices (21 and 22) are formed on a substrate (20) and are each comprised of a plurality of printed components (23 and 24). At least one such printed component (25) is shared by both such semiconductor devices.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 17, 2007
    Assignee: Motorola, Inc.
    Inventors: Hakeem B. Adewole, Paul W. Brazis, Daniel R. Gamota, Jerzy Wielgus, Jie Zhang
  • Patent number: 7030666
    Abstract: An organic semiconductor inverting circuit includes at least three organic transistors, an output terminal (110, 210, 310, 410), a reference supply voltage input (115, 215, 315, 415), a first positive supply voltage input (120, 220, 320, 420), and a negative supply voltage input (125, 225, 325, 425). One of the three organic transistors is an input transistor having a gate to which is coupled an input terminal (105, 205, 305, 405). The output terminal (110, 210, 310, 410) is coupled to a first electrode of at least one of the at least three organic transistors.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 18, 2006
    Assignee: Motorola, Inc.
    Inventors: Paul W. Brazis, Hakeem B. Adewole, Daniel R. Gamota, Jie Zhang
  • Publication number: 20040266054
    Abstract: An exemplary system and method for defining fine printed OFET features is disclosed as comprising inter alia: printed deposition of a conductive material on a substrate; and laser-assisted ablative removal of at least a portion of the conductive material to define source and drain electrode structures. Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve OFET feature definition. Exemplary embodiments of the present invention representatively provide for resolved OFET channel features that may be readily integrated with or extended to other organic electronic technologies for the improvement of device package form factors, weights and other manufacturing and/or device performance metrics.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Paul W. Brazis, Daniel R. Gamota, Krishna Kalyanasundaram, Jie Zhang
  • Patent number: 6677607
    Abstract: A semiconductor device having a flexible or rigid substrate (11) having a gate electrode (21), a source electrode (61 and 101), and a drain electrode (62 and 102) formed thereon and organic semiconductor material (51, 81, and 91) disposed at least partially thereover. The gate electrode (21) has a thin dielectric layer 41 formed thereabout through oxidation. In many of the embodiments, any of the above elements can be formed through contact or non-contact printing. Sizing of the resultant device can be readily scaled to suit various needs.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: January 13, 2004
    Assignee: Motorola, Inc.
    Inventors: Steven M. Scheifers, Daniel R. Gamota, Paul W. Brazis, Jr., Jie Zhang, Lawrence E. Lach
  • Patent number: 6603141
    Abstract: A semiconductor device formed of a flexible or rigid substrate (10) having a gate electrode (11), a source electrode (12), and a drain electrode (13) formed thereon and organic semiconductor material (14) disposed at least partially thereover. With appropriate selection of material, the gate electrode (11) will form a Schottky junction and an ohmic contact will form between the organic semiconductor material (14) and each of the source electrode (12) and drain electrode (13). In many of the embodiments, any of the above elements can be formed through contact or non-contact printing. Sizing of the resultant device can be readily scaled to suit various needs.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 5, 2003
    Assignee: Motorola, Inc.
    Inventors: Lawrence E. Lach, Steven M. Scheifers, Jie Zhang, Daniel R. Gamota, Paul W. Brazis, Jr.